{"id":"https://openalex.org/W1546287554","doi":"https://doi.org/10.1007/bfb0055253","title":"A hardware/software co-design environment for reconfigurable logic systems","display_name":"A hardware/software co-design environment for reconfigurable logic systems","publication_year":1998,"publication_date":"1998-01-01","ids":{"openalex":"https://openalex.org/W1546287554","doi":"https://doi.org/10.1007/bfb0055253","mag":"1546287554"},"language":"en","primary_location":{"id":"doi:10.1007/bfb0055253","is_oa":false,"landing_page_url":"https://doi.org/10.1007/bfb0055253","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},"type":"book-chapter","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5006064112","display_name":"Gordon McGregor","orcid":null},"institutions":[{"id":"https://openalex.org/I181647926","display_name":"University of Strathclyde","ror":"https://ror.org/00n3w3b69","country_code":"GB","type":"education","lineage":["https://openalex.org/I181647926"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Gordon McGregor","raw_affiliation_strings":["Dept. of Electronic and Electrical Engineering, University of Strathclyde, 204 George Street, G1 1XW, Glasgow, UK","University of Strathclyde"],"affiliations":[{"raw_affiliation_string":"Dept. of Electronic and Electrical Engineering, University of Strathclyde, 204 George Street, G1 1XW, Glasgow, UK","institution_ids":["https://openalex.org/I181647926"]},{"raw_affiliation_string":"University of Strathclyde","institution_ids":["https://openalex.org/I181647926"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000551567","display_name":"David Robinson","orcid":"https://orcid.org/0000-0002-7365-510X"},"institutions":[{"id":"https://openalex.org/I181647926","display_name":"University of Strathclyde","ror":"https://ror.org/00n3w3b69","country_code":"GB","type":"education","lineage":["https://openalex.org/I181647926"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"David Robinson","raw_affiliation_strings":["Dept. of Electronic and Electrical Engineering, University of Strathclyde, 204 George Street, G1 1XW, Glasgow, UK","University of Strathclyde"],"affiliations":[{"raw_affiliation_string":"Dept. of Electronic and Electrical Engineering, University of Strathclyde, 204 George Street, G1 1XW, Glasgow, UK","institution_ids":["https://openalex.org/I181647926"]},{"raw_affiliation_string":"University of Strathclyde","institution_ids":["https://openalex.org/I181647926"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5070921981","display_name":"Patrick Lysaght","orcid":null},"institutions":[{"id":"https://openalex.org/I181647926","display_name":"University of Strathclyde","ror":"https://ror.org/00n3w3b69","country_code":"GB","type":"education","lineage":["https://openalex.org/I181647926"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Patrick Lysaght","raw_affiliation_strings":["Dept. of Electronic and Electrical Engineering, University of Strathclyde, 204 George Street, G1 1XW, Glasgow, UK","University of Strathclyde"],"affiliations":[{"raw_affiliation_string":"Dept. of Electronic and Electrical Engineering, University of Strathclyde, 204 George Street, G1 1XW, Glasgow, UK","institution_ids":["https://openalex.org/I181647926"]},{"raw_affiliation_string":"University of Strathclyde","institution_ids":["https://openalex.org/I181647926"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5006064112"],"corresponding_institution_ids":["https://openalex.org/I181647926"],"apc_list":{"value":5000,"currency":"EUR","value_usd":5392},"apc_paid":null,"fwci":2.1294,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.87386216,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"258","last_page":"267"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9950000047683716,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7799359560012817},{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.7788242101669312},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.5921420454978943},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5622328519821167},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5260840654373169},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5181040167808533},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.5165966749191284},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.47326233983039856},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.41855186223983765},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.195236474275589},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.1430935263633728}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7799359560012817},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.7788242101669312},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.5921420454978943},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5622328519821167},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5260840654373169},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5181040167808533},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.5165966749191284},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.47326233983039856},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.41855186223983765},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.195236474275589},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.1430935263633728},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1007/bfb0055253","is_oa":false,"landing_page_url":"https://doi.org/10.1007/bfb0055253","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.19.4518","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.19.4518","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://oak.eee.strath.ac.uk/papers/gmcg_fpl98.ps","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5400000214576721,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1502116401","https://openalex.org/W1526693219","https://openalex.org/W1582559492","https://openalex.org/W1817086147","https://openalex.org/W2097451609","https://openalex.org/W2108873118","https://openalex.org/W2133301618","https://openalex.org/W2155008270","https://openalex.org/W2493513412"],"related_works":["https://openalex.org/W2993910401","https://openalex.org/W1612076744","https://openalex.org/W2014165129","https://openalex.org/W2152074211","https://openalex.org/W2126857316","https://openalex.org/W2129019972","https://openalex.org/W3164085601","https://openalex.org/W1522032972","https://openalex.org/W2139962137","https://openalex.org/W2113308450"],"abstract_inverted_index":null,"counts_by_year":[{"year":2021,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}