{"id":"https://openalex.org/W2004037509","doi":"https://doi.org/10.1007/bf02960763","title":"BIST design for detecting multiple stuck-open faults in CMOS circuits using transition count","display_name":"BIST design for detecting multiple stuck-open faults in CMOS circuits using transition count","publication_year":2002,"publication_date":"2002-11-01","ids":{"openalex":"https://openalex.org/W2004037509","doi":"https://doi.org/10.1007/bf02960763","mag":"2004037509"},"language":"en","primary_location":{"id":"doi:10.1007/bf02960763","is_oa":false,"landing_page_url":"https://doi.org/10.1007/bf02960763","pdf_url":null,"source":{"id":"https://openalex.org/S161516442","display_name":"Journal of Computer Science and Technology","issn_l":"1000-9000","issn":["1000-9000","1860-4749"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Computer Science and Technology","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5082934529","display_name":"Hafizur Rahaman","orcid":"https://orcid.org/0000-0001-9012-5437"},"institutions":[{"id":"https://openalex.org/I26072440","display_name":"Indian Institute of Information Technology Allahabad","ror":"https://ror.org/03rgjt374","country_code":"IN","type":"education","lineage":["https://openalex.org/I26072440"]},{"id":"https://openalex.org/I71495548","display_name":"Indian Institute of Management Calcutta","ror":"https://ror.org/02zhewk16","country_code":"IN","type":"education","lineage":["https://openalex.org/I71495548"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Hafizur Rahaman","raw_affiliation_strings":["Indian Institute of Information Technology, 700 106, Calcutta, India","Indian Institute of Information Technology, Calcutta-700 106, India#TAB#"],"affiliations":[{"raw_affiliation_string":"Indian Institute of Information Technology, 700 106, Calcutta, India","institution_ids":["https://openalex.org/I71495548","https://openalex.org/I26072440"]},{"raw_affiliation_string":"Indian Institute of Information Technology, Calcutta-700 106, India#TAB#","institution_ids":["https://openalex.org/I26072440"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059700720","display_name":"Debesh K. Das","orcid":"https://orcid.org/0000-0003-1736-1497"},"institutions":[{"id":"https://openalex.org/I170979836","display_name":"Jadavpur University","ror":"https://ror.org/02af4h012","country_code":"IN","type":"education","lineage":["https://openalex.org/I170979836"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Debesh K. Das","raw_affiliation_strings":["Department of Computer Science and Engineering, Jadavpur University, 700 032, Calcutta, India","Department of Computer Science and Engineering, Jadavpur University, Calcutta, 700 032, India"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Jadavpur University, 700 032, Calcutta, India","institution_ids":["https://openalex.org/I170979836"]},{"raw_affiliation_string":"Department of Computer Science and Engineering, Jadavpur University, Calcutta, 700 032, India","institution_ids":["https://openalex.org/I170979836"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5067730042","display_name":"Bhargab B. Bhattacharya","orcid":"https://orcid.org/0000-0002-5890-2483"},"institutions":[{"id":"https://openalex.org/I6498739","display_name":"Indian Statistical Institute","ror":"https://ror.org/00q2w1j53","country_code":"IN","type":"education","lineage":["https://openalex.org/I6498739"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Bhargab B. Bhattacharya","raw_affiliation_strings":["ACM Unit, Indian Statistical Institute, 700 108, Calcutta, India","ACM Unit Indian Statistical Institute, Calcutta 700 108, India;"],"affiliations":[{"raw_affiliation_string":"ACM Unit, Indian Statistical Institute, 700 108, Calcutta, India","institution_ids":["https://openalex.org/I6498739"]},{"raw_affiliation_string":"ACM Unit Indian Statistical Institute, Calcutta 700 108, India;","institution_ids":["https://openalex.org/I6498739"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5082934529"],"corresponding_institution_ids":["https://openalex.org/I26072440","https://openalex.org/I71495548"],"apc_list":{"value":2290,"currency":"EUR","value_usd":2890},"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.10164365,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"17","issue":"6","first_page":"731","last_page":"737"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/built-in-self-test","display_name":"Built-in self-test","score":0.687238335609436},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6483737230300903},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6128976345062256},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.5468868017196655},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.5096688270568848},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.48785877227783203},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.4873098134994507},{"id":"https://openalex.org/keywords/digital-pattern-generator","display_name":"Digital pattern generator","score":0.4835336208343506},{"id":"https://openalex.org/keywords/signature","display_name":"Signature (topology)","score":0.4806719720363617},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.479205459356308},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.46875524520874023},{"id":"https://openalex.org/keywords/shift-register","display_name":"Shift register","score":0.46575623750686646},{"id":"https://openalex.org/keywords/generator","display_name":"Generator (circuit theory)","score":0.44984671473503113},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4095574617385864},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3980058431625366},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.35508447885513306},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3480299115180969},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.2701628804206848},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.23303446173667908},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1881246268749237},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.16614437103271484},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13555535674095154},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.10740137100219727},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08233997225761414}],"concepts":[{"id":"https://openalex.org/C2780980493","wikidata":"https://www.wikidata.org/wiki/Q181142","display_name":"Built-in self-test","level":2,"score":0.687238335609436},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6483737230300903},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6128976345062256},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.5468868017196655},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.5096688270568848},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.48785877227783203},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.4873098134994507},{"id":"https://openalex.org/C151346624","wikidata":"https://www.wikidata.org/wiki/Q5276129","display_name":"Digital pattern generator","level":3,"score":0.4835336208343506},{"id":"https://openalex.org/C2779696439","wikidata":"https://www.wikidata.org/wiki/Q7512811","display_name":"Signature (topology)","level":2,"score":0.4806719720363617},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.479205459356308},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.46875524520874023},{"id":"https://openalex.org/C49654631","wikidata":"https://www.wikidata.org/wiki/Q746165","display_name":"Shift register","level":3,"score":0.46575623750686646},{"id":"https://openalex.org/C2780992000","wikidata":"https://www.wikidata.org/wiki/Q17016113","display_name":"Generator (circuit theory)","level":3,"score":0.44984671473503113},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4095574617385864},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3980058431625366},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.35508447885513306},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3480299115180969},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.2701628804206848},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.23303446173667908},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1881246268749237},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.16614437103271484},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13555535674095154},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.10740137100219727},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08233997225761414},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/bf02960763","is_oa":false,"landing_page_url":"https://doi.org/10.1007/bf02960763","pdf_url":null,"source":{"id":"https://openalex.org/S161516442","display_name":"Journal of Computer Science and Technology","issn_l":"1000-9000","issn":["1000-9000","1860-4749"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of Computer Science and Technology","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/13","score":0.5099999904632568,"display_name":"Climate action"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":23,"referenced_works":["https://openalex.org/W36314620","https://openalex.org/W156549128","https://openalex.org/W1777422625","https://openalex.org/W1967664042","https://openalex.org/W2029357904","https://openalex.org/W2041406712","https://openalex.org/W2043905562","https://openalex.org/W2046817879","https://openalex.org/W2058273005","https://openalex.org/W2064119288","https://openalex.org/W2082758488","https://openalex.org/W2083783920","https://openalex.org/W2088047732","https://openalex.org/W2097792565","https://openalex.org/W2098415526","https://openalex.org/W2100291420","https://openalex.org/W2129657598","https://openalex.org/W2141114760","https://openalex.org/W2157111192","https://openalex.org/W2165186270","https://openalex.org/W2542612625","https://openalex.org/W4248583419","https://openalex.org/W4285718364"],"related_works":["https://openalex.org/W2188176208","https://openalex.org/W2123022840","https://openalex.org/W2105858357","https://openalex.org/W2914537975","https://openalex.org/W1859800149","https://openalex.org/W2119351822","https://openalex.org/W2118970729","https://openalex.org/W4288754393","https://openalex.org/W2097599816","https://openalex.org/W2080947141"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2026-01-15T23:16:33.117629","created_date":"2025-10-10T00:00:00"}
