{"id":"https://openalex.org/W1993140587","doi":"https://doi.org/10.1007/bf02427794","title":"An efficient bit-level systolic cell design for finite ring digital signal processing applications","display_name":"An efficient bit-level systolic cell design for finite ring digital signal processing applications","publication_year":1989,"publication_date":"1989-09-01","ids":{"openalex":"https://openalex.org/W1993140587","doi":"https://doi.org/10.1007/bf02427794","mag":"1993140587"},"language":"en","primary_location":{"id":"doi:10.1007/bf02427794","is_oa":false,"landing_page_url":"https://doi.org/10.1007/bf02427794","pdf_url":null,"source":{"id":"https://openalex.org/S4210233059","display_name":"The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology","issn_l":"0922-5773","issn":["0922-5773","1573-109X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of VLSI signal processing systems for signal, image and video technology","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5007393900","display_name":"G.A. Jullien","orcid":"https://orcid.org/0009-0009-0911-2926"},"institutions":[{"id":"https://openalex.org/I74413500","display_name":"University of Windsor","ror":"https://ror.org/01gw3d370","country_code":"CA","type":"education","lineage":["https://openalex.org/I74413500"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"G. A. Jullien","raw_affiliation_strings":["VLSI Research Group, University of Windsor, N9B 3P4, Windsor, Ontario, Canada","VLSI Research Group, University of Windsor, Windsor, Canada N9B 3P4#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"VLSI Research Group, University of Windsor, N9B 3P4, Windsor, Ontario, Canada","institution_ids":["https://openalex.org/I74413500"]},{"raw_affiliation_string":"VLSI Research Group, University of Windsor, Windsor, Canada N9B 3P4#TAB#","institution_ids":["https://openalex.org/I74413500"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033491359","display_name":"Peter D. Bird","orcid":null},"institutions":[{"id":"https://openalex.org/I153908563","display_name":"Nortel (Canada)","ror":"https://ror.org/03rz4pm90","country_code":"CA","type":"company","lineage":["https://openalex.org/I153908563"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"P. D. Bird","raw_affiliation_strings":["Northern Telecom, Ottawa, Canada","Northern Telecom, Ottawa, Canada#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Northern Telecom, Ottawa, Canada","institution_ids":["https://openalex.org/I153908563"]},{"raw_affiliation_string":"Northern Telecom, Ottawa, Canada#TAB#","institution_ids":["https://openalex.org/I153908563"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087452883","display_name":"J. T. Carr","orcid":null},"institutions":[{"id":"https://openalex.org/I176714629","display_name":"Bell (Canada)","ror":"https://ror.org/00xdg8m59","country_code":"CA","type":"company","lineage":["https://openalex.org/I176714629"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"J. T. Carr","raw_affiliation_strings":["Bell-Northern Research, Ottawa, Canada","Bell-Northern Res., Ottawa, Canada#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Bell-Northern Research, Ottawa, Canada","institution_ids":["https://openalex.org/I176714629"]},{"raw_affiliation_string":"Bell-Northern Res., Ottawa, Canada#TAB#","institution_ids":["https://openalex.org/I176714629"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084212906","display_name":"M. Taheri","orcid":null},"institutions":[{"id":"https://openalex.org/I176714629","display_name":"Bell (Canada)","ror":"https://ror.org/00xdg8m59","country_code":"CA","type":"company","lineage":["https://openalex.org/I176714629"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"M. Taheri","raw_affiliation_strings":["Bell-Northern Research, Ottawa, Canada","Bell-Northern Res., Ottawa, Canada#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Bell-Northern Research, Ottawa, Canada","institution_ids":["https://openalex.org/I176714629"]},{"raw_affiliation_string":"Bell-Northern Res., Ottawa, Canada#TAB#","institution_ids":["https://openalex.org/I176714629"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5056245742","display_name":"William C. Miller","orcid":"https://orcid.org/0000-0002-1934-7827"},"institutions":[{"id":"https://openalex.org/I74413500","display_name":"University of Windsor","ror":"https://ror.org/01gw3d370","country_code":"CA","type":"education","lineage":["https://openalex.org/I74413500"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"W. C. Miller","raw_affiliation_strings":["VLSI Research Group, University of Windsor, N9B 3P4, Windsor, Ontario, Canada","VLSI Research Group, University of Windsor, Windsor, Canada N9B 3P4#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"VLSI Research Group, University of Windsor, N9B 3P4, Windsor, Ontario, Canada","institution_ids":["https://openalex.org/I74413500"]},{"raw_affiliation_string":"VLSI Research Group, University of Windsor, Windsor, Canada N9B 3P4#TAB#","institution_ids":["https://openalex.org/I74413500"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":4.5542,"has_fulltext":false,"cited_by_count":31,"citation_normalized_percentile":{"value":0.94273901,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":null,"biblio":{"volume":"1","issue":"3","first_page":"189","last_page":"207"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11130","display_name":"Coding theory and cryptography","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.6409249305725098},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6327738165855408},{"id":"https://openalex.org/keywords/systolic-array","display_name":"Systolic array","score":0.6168661713600159},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.6131144165992737},{"id":"https://openalex.org/keywords/binary-number","display_name":"Binary number","score":0.5406993627548218},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.49354374408721924},{"id":"https://openalex.org/keywords/signal-processing","display_name":"Signal processing","score":0.45577266812324524},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.42227989435195923},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.37778812646865845},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3400011658668518},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.32648342847824097},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.29863178730010986},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.28236526250839233},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.25119882822036743},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.20796802639961243},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16906675696372986}],"concepts":[{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.6409249305725098},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6327738165855408},{"id":"https://openalex.org/C150741067","wikidata":"https://www.wikidata.org/wiki/Q2377218","display_name":"Systolic array","level":3,"score":0.6168661713600159},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.6131144165992737},{"id":"https://openalex.org/C48372109","wikidata":"https://www.wikidata.org/wiki/Q3913","display_name":"Binary number","level":2,"score":0.5406993627548218},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.49354374408721924},{"id":"https://openalex.org/C104267543","wikidata":"https://www.wikidata.org/wiki/Q208163","display_name":"Signal processing","level":3,"score":0.45577266812324524},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.42227989435195923},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.37778812646865845},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3400011658668518},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.32648342847824097},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.29863178730010986},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.28236526250839233},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.25119882822036743},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.20796802639961243},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16906675696372986},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/bf02427794","is_oa":false,"landing_page_url":"https://doi.org/10.1007/bf02427794","pdf_url":null,"source":{"id":"https://openalex.org/S4210233059","display_name":"The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology","issn_l":"0922-5773","issn":["0922-5773","1573-109X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of VLSI signal processing systems for signal, image and video technology","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4699999988079071,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320334593","display_name":"Natural Sciences and Engineering Research Council of Canada","ror":"https://ror.org/01h531d29"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W50665834","https://openalex.org/W1489433220","https://openalex.org/W1564080326","https://openalex.org/W1696310287","https://openalex.org/W1999448593","https://openalex.org/W2010126845","https://openalex.org/W2017369466","https://openalex.org/W2020141429","https://openalex.org/W2027750498","https://openalex.org/W2029156468","https://openalex.org/W2064130185","https://openalex.org/W2086721470","https://openalex.org/W2095296829","https://openalex.org/W2096491513","https://openalex.org/W2117620586","https://openalex.org/W2123008137","https://openalex.org/W2149080859","https://openalex.org/W4285719527","https://openalex.org/W6600578647"],"related_works":["https://openalex.org/W2183015194","https://openalex.org/W4210376836","https://openalex.org/W4210925376","https://openalex.org/W1633995705","https://openalex.org/W2596211269","https://openalex.org/W197862639","https://openalex.org/W2360384790","https://openalex.org/W1977407858","https://openalex.org/W4232397253","https://openalex.org/W4235913033"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2026-06-19T15:47:20.252518","created_date":"2025-10-10T00:00:00"}