{"id":"https://openalex.org/W2033941027","doi":"https://doi.org/10.1007/bf01383876","title":"Translating VHDL into functional symbolic finite-state models","display_name":"Translating VHDL into functional symbolic finite-state models","publication_year":1995,"publication_date":"1995-08-01","ids":{"openalex":"https://openalex.org/W2033941027","doi":"https://doi.org/10.1007/bf01383876","mag":"2033941027"},"language":"en","primary_location":{"id":"doi:10.1007/bf01383876","is_oa":false,"landing_page_url":"https://doi.org/10.1007/bf01383876","pdf_url":null,"source":{"id":"https://openalex.org/S3845260","display_name":"Formal Methods in System Design","issn_l":"0925-9856","issn":["0925-9856","1572-8102"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Formal Methods in System Design","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5097430162","display_name":"Gert D\ufffdhmen","orcid":null},"institutions":[{"id":"https://openalex.org/I202367325","display_name":"Oldenburger Institut f\u00fcr Informatik","ror":"https://ror.org/003sav189","country_code":"DE","type":"facility","lineage":["https://openalex.org/I202367325"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Gert D\ufffdhmen","raw_affiliation_strings":["OFFIS Oldenburg, Germany"],"affiliations":[{"raw_affiliation_string":"OFFIS Oldenburg, Germany","institution_ids":["https://openalex.org/I202367325"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053694194","display_name":"Ronald Herrmann","orcid":null},"institutions":[{"id":"https://openalex.org/I202367325","display_name":"Oldenburger Institut f\u00fcr Informatik","ror":"https://ror.org/003sav189","country_code":"DE","type":"facility","lineage":["https://openalex.org/I202367325"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Ronald Herrmann","raw_affiliation_strings":["OFFIS, Westerstra\u00dfe 10-12, 26121, Oldenburg, Germany","OFFIS Oldenburg, Germany"],"affiliations":[{"raw_affiliation_string":"OFFIS, Westerstra\u00dfe 10-12, 26121, Oldenburg, Germany","institution_ids":["https://openalex.org/I202367325"]},{"raw_affiliation_string":"OFFIS Oldenburg, Germany","institution_ids":["https://openalex.org/I202367325"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5084259726","display_name":"Hergen Pargmann","orcid":null},"institutions":[{"id":"https://openalex.org/I129877168","display_name":"Carl von Ossietzky Universit\u00e4t Oldenburg","ror":"https://ror.org/033n9gh91","country_code":"DE","type":"education","lineage":["https://openalex.org/I129877168"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Hergen Pargmann","raw_affiliation_strings":["University of Oldenburg, Ammerl\u00e4nder Heerstra\u00dfe 114-118, 26111, Oldenburg, Germany","University of Oldenburg, Oldenburg, Germany"],"affiliations":[{"raw_affiliation_string":"University of Oldenburg, Ammerl\u00e4nder Heerstra\u00dfe 114-118, 26111, Oldenburg, Germany","institution_ids":["https://openalex.org/I129877168"]},{"raw_affiliation_string":"University of Oldenburg, Oldenburg, Germany","institution_ids":["https://openalex.org/I129877168"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5097430162"],"corresponding_institution_ids":["https://openalex.org/I202367325"],"apc_list":{"value":2690,"currency":"EUR","value_usd":3490},"apc_paid":null,"fwci":1.6556,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.8575335,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"7","issue":"1-2","first_page":"125","last_page":"148"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7472267150878906},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.7160282135009766},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.6579471826553345},{"id":"https://openalex.org/keywords/representation","display_name":"Representation (politics)","score":0.6573566794395447},{"id":"https://openalex.org/keywords/finite-state-machine","display_name":"Finite-state machine","score":0.6377153992652893},{"id":"https://openalex.org/keywords/semantics","display_name":"Semantics (computer science)","score":0.5961360335350037},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.5508395433425903},{"id":"https://openalex.org/keywords/model-checking","display_name":"Model checking","score":0.5485858917236328},{"id":"https://openalex.org/keywords/symbolic-data-analysis","display_name":"Symbolic data analysis","score":0.5327019691467285},{"id":"https://openalex.org/keywords/automaton","display_name":"Automaton","score":0.48520854115486145},{"id":"https://openalex.org/keywords/intermediate-language","display_name":"Intermediate language","score":0.4754481017589569},{"id":"https://openalex.org/keywords/state","display_name":"State (computer science)","score":0.460613489151001},{"id":"https://openalex.org/keywords/symbolic-execution","display_name":"Symbolic execution","score":0.44854918122291565},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.15619829297065735},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.1347053050994873},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.09909811615943909},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.09387409687042236}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7472267150878906},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.7160282135009766},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.6579471826553345},{"id":"https://openalex.org/C2776359362","wikidata":"https://www.wikidata.org/wiki/Q2145286","display_name":"Representation (politics)","level":3,"score":0.6573566794395447},{"id":"https://openalex.org/C167822520","wikidata":"https://www.wikidata.org/wiki/Q176452","display_name":"Finite-state machine","level":2,"score":0.6377153992652893},{"id":"https://openalex.org/C184337299","wikidata":"https://www.wikidata.org/wiki/Q1437428","display_name":"Semantics (computer science)","level":2,"score":0.5961360335350037},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.5508395433425903},{"id":"https://openalex.org/C110251889","wikidata":"https://www.wikidata.org/wiki/Q1569697","display_name":"Model checking","level":2,"score":0.5485858917236328},{"id":"https://openalex.org/C65620979","wikidata":"https://www.wikidata.org/wiki/Q7661176","display_name":"Symbolic data analysis","level":2,"score":0.5327019691467285},{"id":"https://openalex.org/C112505250","wikidata":"https://www.wikidata.org/wiki/Q787116","display_name":"Automaton","level":2,"score":0.48520854115486145},{"id":"https://openalex.org/C77660490","wikidata":"https://www.wikidata.org/wiki/Q244916","display_name":"Intermediate language","level":3,"score":0.4754481017589569},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.460613489151001},{"id":"https://openalex.org/C2779639559","wikidata":"https://www.wikidata.org/wiki/Q7661178","display_name":"Symbolic execution","level":3,"score":0.44854918122291565},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.15619829297065735},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.1347053050994873},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.09909811615943909},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.09387409687042236},{"id":"https://openalex.org/C17744445","wikidata":"https://www.wikidata.org/wiki/Q36442","display_name":"Political science","level":0,"score":0.0},{"id":"https://openalex.org/C199539241","wikidata":"https://www.wikidata.org/wiki/Q7748","display_name":"Law","level":1,"score":0.0},{"id":"https://openalex.org/C94625758","wikidata":"https://www.wikidata.org/wiki/Q7163","display_name":"Politics","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/bf01383876","is_oa":false,"landing_page_url":"https://doi.org/10.1007/bf01383876","pdf_url":null,"source":{"id":"https://openalex.org/S3845260","display_name":"Formal Methods in System Design","issn_l":"0925-9856","issn":["0925-9856","1572-8102"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Formal Methods in System Design","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":28,"referenced_works":["https://openalex.org/W65125029","https://openalex.org/W1501834391","https://openalex.org/W1505685495","https://openalex.org/W1517173520","https://openalex.org/W1525623009","https://openalex.org/W1531074653","https://openalex.org/W1539846388","https://openalex.org/W1550110278","https://openalex.org/W1966926494","https://openalex.org/W1972065960","https://openalex.org/W1976654267","https://openalex.org/W1994143452","https://openalex.org/W2061438988","https://openalex.org/W2080267935","https://openalex.org/W2096820312","https://openalex.org/W2114092850","https://openalex.org/W2119469280","https://openalex.org/W2135453964","https://openalex.org/W2144588028","https://openalex.org/W2149479807","https://openalex.org/W2150119568","https://openalex.org/W2152691384","https://openalex.org/W2163101554","https://openalex.org/W2164159084","https://openalex.org/W2169321900","https://openalex.org/W2480147692","https://openalex.org/W2538844384","https://openalex.org/W4235269005"],"related_works":["https://openalex.org/W146887057","https://openalex.org/W2391435730","https://openalex.org/W2381282135","https://openalex.org/W2384030275","https://openalex.org/W2019299443","https://openalex.org/W345638404","https://openalex.org/W4245197793","https://openalex.org/W1994915990","https://openalex.org/W4200059639","https://openalex.org/W2101264565"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}