{"id":"https://openalex.org/W1974996798","doi":"https://doi.org/10.1007/bf01383833","title":"Signal transition graph constraints for synthesis of hazard-free asynchronous circuits with unbounded-gate delays","display_name":"Signal transition graph constraints for synthesis of hazard-free asynchronous circuits with unbounded-gate delays","publication_year":1994,"publication_date":"1994-12-01","ids":{"openalex":"https://openalex.org/W1974996798","doi":"https://doi.org/10.1007/bf01383833","mag":"1974996798"},"language":"en","primary_location":{"id":"doi:10.1007/bf01383833","is_oa":false,"landing_page_url":"https://doi.org/10.1007/bf01383833","pdf_url":null,"source":{"id":"https://openalex.org/S3845260","display_name":"Formal Methods in System Design","issn_l":"0925-9856","issn":["0925-9856","1572-8102"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Formal Methods in System Design","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5026734295","display_name":"R. Nagalla","orcid":null},"institutions":[{"id":"https://openalex.org/I31746571","display_name":"UNSW Sydney","ror":"https://ror.org/03r8z3t63","country_code":"AU","type":"education","lineage":["https://openalex.org/I31746571"]}],"countries":["AU"],"is_corresponding":false,"raw_author_name":"Radhakrishna Nagalla","raw_affiliation_strings":["Computer and Systems Technology Laboratory, School of Computer Science and Engineering, University of New South Wales, 2052, NSW, Australia","Computer and Systems Technology Laboratory, School of Computer Science and Engineering, University of New South Wales, Australia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer and Systems Technology Laboratory, School of Computer Science and Engineering, University of New South Wales, 2052, NSW, Australia","institution_ids":["https://openalex.org/I31746571"]},{"raw_affiliation_string":"Computer and Systems Technology Laboratory, School of Computer Science and Engineering, University of New South Wales, Australia","institution_ids":["https://openalex.org/I31746571"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5069433294","display_name":"G.R. Hellestrand","orcid":null},"institutions":[{"id":"https://openalex.org/I31746571","display_name":"UNSW Sydney","ror":"https://ror.org/03r8z3t63","country_code":"AU","type":"education","lineage":["https://openalex.org/I31746571"]}],"countries":["AU"],"is_corresponding":false,"raw_author_name":"Graham Hellestrand","raw_affiliation_strings":["Computer and Systems Technology Laboratory, School of Computer Science and Engineering, University of New South Wales, 2052, NSW, Australia","Computer and Systems Technology Laboratory, School of Computer Science and Engineering, University of New South Wales, Australia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Computer and Systems Technology Laboratory, School of Computer Science and Engineering, University of New South Wales, 2052, NSW, Australia","institution_ids":["https://openalex.org/I31746571"]},{"raw_affiliation_string":"Computer and Systems Technology Laboratory, School of Computer Science and Engineering, University of New South Wales, Australia","institution_ids":["https://openalex.org/I31746571"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":{"value":2690,"currency":"EUR","value_usd":3490},"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.09384679,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"5","issue":"3","first_page":"245","last_page":"273"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11125","display_name":"Petri Nets in System Modeling","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.8199288249015808},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.622247040271759},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.5860562920570374},{"id":"https://openalex.org/keywords/coding","display_name":"Coding (social sciences)","score":0.553030788898468},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5091614127159119},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.45740747451782227},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.427762508392334},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.4248579740524292},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.4229496121406555},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.24361836910247803},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.16953110694885254},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10916844010353088},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.09850925207138062},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.07546404004096985},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.06650212407112122}],"concepts":[{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.8199288249015808},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.622247040271759},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.5860562920570374},{"id":"https://openalex.org/C179518139","wikidata":"https://www.wikidata.org/wiki/Q5140297","display_name":"Coding (social sciences)","level":2,"score":0.553030788898468},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5091614127159119},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.45740747451782227},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.427762508392334},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.4248579740524292},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.4229496121406555},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.24361836910247803},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.16953110694885254},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10916844010353088},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.09850925207138062},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.07546404004096985},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.06650212407112122},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1007/bf01383833","is_oa":false,"landing_page_url":"https://doi.org/10.1007/bf01383833","pdf_url":null,"source":{"id":"https://openalex.org/S3845260","display_name":"Formal Methods in System Design","issn_l":"0925-9856","issn":["0925-9856","1572-8102"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Formal Methods in System Design","raw_type":"journal-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.52.8888","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.52.8888","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"ftp://ftp.cse.unsw.edu.au/pub/doc/papers/UNSW/9305.ps.Z","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Climate action","score":0.8700000047683716,"id":"https://metadata.un.org/sdg/13"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320322725","display_name":"China Scholarship Council","ror":"https://ror.org/04atp4p48"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1552934489","https://openalex.org/W1554812212","https://openalex.org/W1828764349","https://openalex.org/W1993742654","https://openalex.org/W1996109622","https://openalex.org/W2033724727","https://openalex.org/W2068247526","https://openalex.org/W2118818031","https://openalex.org/W2120519502","https://openalex.org/W2140792504","https://openalex.org/W2155533101","https://openalex.org/W2544595046","https://openalex.org/W4255548486"],"related_works":["https://openalex.org/W1948903516","https://openalex.org/W2085028021","https://openalex.org/W2187164010","https://openalex.org/W4312516786","https://openalex.org/W2138474603","https://openalex.org/W3094139610","https://openalex.org/W1993985975","https://openalex.org/W937897205","https://openalex.org/W2146990170","https://openalex.org/W2380707529"],"abstract_inverted_index":null,"counts_by_year":[{"year":2019,"cited_by_count":1}],"updated_date":"2026-06-19T17:40:00.097472","created_date":"2025-10-10T00:00:00"}
