{"id":"https://openalex.org/W2054472284","doi":"https://doi.org/10.1007/bf00927836","title":"Control generation in the design of processor arrays","display_name":"Control generation in the design of processor arrays","publication_year":1991,"publication_date":"1991-06-01","ids":{"openalex":"https://openalex.org/W2054472284","doi":"https://doi.org/10.1007/bf00927836","mag":"2054472284"},"language":"en","primary_location":{"id":"doi:10.1007/bf00927836","is_oa":false,"landing_page_url":"https://doi.org/10.1007/bf00927836","pdf_url":null,"source":{"id":"https://openalex.org/S4210233059","display_name":"The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology","issn_l":"0922-5773","issn":["0922-5773","1573-109X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of VLSI signal processing systems for signal, image and video technology","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5076672029","display_name":"J\u00fcrgen Teich","orcid":"https://orcid.org/0000-0001-6285-5862"},"institutions":[{"id":"https://openalex.org/I91712215","display_name":"Saarland University","ror":"https://ror.org/01jdpyv68","country_code":"DE","type":"education","lineage":["https://openalex.org/I91712215"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"J\u00fcrgen Teich","raw_affiliation_strings":["Institute of Microelectronics, University of Saarland, D-6600, Saarbr\u00fccken, West Germany","University of Saarland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, University of Saarland, D-6600, Saarbr\u00fccken, West Germany","institution_ids":["https://openalex.org/I91712215"]},{"raw_affiliation_string":"University of Saarland","institution_ids":["https://openalex.org/I91712215"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5060999697","display_name":"Lothar Thiele","orcid":"https://orcid.org/0000-0001-6139-868X"},"institutions":[{"id":"https://openalex.org/I91712215","display_name":"Saarland University","ror":"https://ror.org/01jdpyv68","country_code":"DE","type":"education","lineage":["https://openalex.org/I91712215"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Lothar Thiele","raw_affiliation_strings":["Institute of Microelectronics, University of Saarland, D-6600, Saarbr\u00fccken, West Germany","University of Saarland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, University of Saarland, D-6600, Saarbr\u00fccken, West Germany","institution_ids":["https://openalex.org/I91712215"]},{"raw_affiliation_string":"University of Saarland","institution_ids":["https://openalex.org/I91712215"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":4.4635,"has_fulltext":false,"cited_by_count":45,"citation_normalized_percentile":{"value":0.94580234,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"3","issue":"1-2","first_page":"77","last_page":"92"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.996399998664856,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9959999918937683,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.675331711769104},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6427844762802124},{"id":"https://openalex.org/keywords/systolic-array","display_name":"Systolic array","score":0.6286864280700684},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.5622990131378174},{"id":"https://openalex.org/keywords/wavefront","display_name":"Wavefront","score":0.5299217104911804},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4174787998199463},{"id":"https://openalex.org/keywords/processor-array","display_name":"Processor array","score":0.41704750061035156},{"id":"https://openalex.org/keywords/class","display_name":"Class (philosophy)","score":0.41609904170036316},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.27715209126472473},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.25004875659942627}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.675331711769104},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6427844762802124},{"id":"https://openalex.org/C150741067","wikidata":"https://www.wikidata.org/wiki/Q2377218","display_name":"Systolic array","level":3,"score":0.6286864280700684},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.5622990131378174},{"id":"https://openalex.org/C165699331","wikidata":"https://www.wikidata.org/wiki/Q461533","display_name":"Wavefront","level":2,"score":0.5299217104911804},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4174787998199463},{"id":"https://openalex.org/C2776189500","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Processor array","level":2,"score":0.41704750061035156},{"id":"https://openalex.org/C2777212361","wikidata":"https://www.wikidata.org/wiki/Q5127848","display_name":"Class (philosophy)","level":2,"score":0.41609904170036316},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.27715209126472473},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.25004875659942627},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C120665830","wikidata":"https://www.wikidata.org/wiki/Q14620","display_name":"Optics","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/bf00927836","is_oa":false,"landing_page_url":"https://doi.org/10.1007/bf00927836","pdf_url":null,"source":{"id":"https://openalex.org/S4210233059","display_name":"The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology","issn_l":"0922-5773","issn":["0922-5773","1573-109X"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Journal of VLSI signal processing systems for signal, image and video technology","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8399999737739563}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":38,"referenced_works":["https://openalex.org/W161315898","https://openalex.org/W1497480144","https://openalex.org/W1509443229","https://openalex.org/W1667077121","https://openalex.org/W1731787423","https://openalex.org/W1963949583","https://openalex.org/W1967675749","https://openalex.org/W1968143987","https://openalex.org/W1974106274","https://openalex.org/W2012497704","https://openalex.org/W2027739182","https://openalex.org/W2047333300","https://openalex.org/W2054388411","https://openalex.org/W2064130185","https://openalex.org/W2076937510","https://openalex.org/W2079092669","https://openalex.org/W2084904853","https://openalex.org/W2087404120","https://openalex.org/W2096046869","https://openalex.org/W2099216186","https://openalex.org/W2099876805","https://openalex.org/W2139378242","https://openalex.org/W2144266482","https://openalex.org/W2146769945","https://openalex.org/W2146928317","https://openalex.org/W2148321174","https://openalex.org/W2152030480","https://openalex.org/W2157118812","https://openalex.org/W2166818774","https://openalex.org/W2170396156","https://openalex.org/W2171603032","https://openalex.org/W2225533031","https://openalex.org/W2505968561","https://openalex.org/W2551143771","https://openalex.org/W2913200164","https://openalex.org/W4234407207","https://openalex.org/W4285719527","https://openalex.org/W4301706555"],"related_works":["https://openalex.org/W1607818992","https://openalex.org/W3144399550","https://openalex.org/W1489640024","https://openalex.org/W2041540577","https://openalex.org/W2045260997","https://openalex.org/W57167696","https://openalex.org/W2076937510","https://openalex.org/W4221072574","https://openalex.org/W1570524756","https://openalex.org/W2001112859"],"abstract_inverted_index":null,"counts_by_year":[{"year":2018,"cited_by_count":1}],"updated_date":"2026-06-19T15:47:20.252518","created_date":"2025-10-10T00:00:00"}
