{"id":"https://openalex.org/W1599129448","doi":"https://doi.org/10.1007/bf00134684","title":"A co-synthesis approach to embedded system design automation","display_name":"A co-synthesis approach to embedded system design automation","publication_year":1996,"publication_date":"1996-01-01","ids":{"openalex":"https://openalex.org/W1599129448","doi":"https://doi.org/10.1007/bf00134684","mag":"1599129448"},"language":"en","primary_location":{"id":"doi:10.1007/bf00134684","is_oa":false,"landing_page_url":"https://doi.org/10.1007/bf00134684","pdf_url":null,"source":{"id":"https://openalex.org/S85498321","display_name":"Design Automation for Embedded Systems","issn_l":"0929-5585","issn":["0929-5585","1572-8080"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Design Automation for Embedded Systems","raw_type":"journal-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5096917158","display_name":"Rajesh K. Gup","orcid":null},"institutions":[{"id":"https://openalex.org/I157725225","display_name":"University of Illinois Urbana-Champaign","ror":"https://ror.org/047426m28","country_code":"US","type":"education","lineage":["https://openalex.org/I157725225"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Rajesh K. Gup","raw_affiliation_strings":["Department of Computer Science, University of Illinois, Urbana-Champaign 1304 W. Springfield Avenue, 61801, Urbana, IL, USA","DEPARTMENT OF COMPUTER SCIENCE, UNIVERSITY OF ILLINOIS URBANA, USA#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, University of Illinois, Urbana-Champaign 1304 W. Springfield Avenue, 61801, Urbana, IL, USA","institution_ids":["https://openalex.org/I157725225"]},{"raw_affiliation_string":"DEPARTMENT OF COMPUTER SCIENCE, UNIVERSITY OF ILLINOIS URBANA, USA#TAB#","institution_ids":["https://openalex.org/I157725225"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5072927296","display_name":"Giovanni De Micheli","orcid":"https://orcid.org/0000-0002-7827-3215"},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Giovanni de Micheli","raw_affiliation_strings":["Department of Electrical Engineering, Stanford University, 94305, Stanford, CA, USA","Department of Electrical Engineering, Stanford University , Stanford, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Stanford University, 94305, Stanford, CA, USA","institution_ids":["https://openalex.org/I97018004"]},{"raw_affiliation_string":"Department of Electrical Engineering, Stanford University , Stanford, USA","institution_ids":["https://openalex.org/I97018004"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":{"value":3590,"currency":"USD","value_usd":3590},"apc_paid":null,"fwci":9.8137,"has_fulltext":false,"cited_by_count":56,"citation_normalized_percentile":{"value":0.98213146,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"1","issue":"1-2","first_page":"69","last_page":"120"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8289110660552979},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.5379323363304138},{"id":"https://openalex.org/keywords/probabilistic-logic","display_name":"Probabilistic logic","score":0.5255288481712341},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.4965561032295227},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.48122334480285645},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.48012304306030273},{"id":"https://openalex.org/keywords/decomposition","display_name":"Decomposition","score":0.4783334732055664},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.46144384145736694},{"id":"https://openalex.org/keywords/automation","display_name":"Automation","score":0.4499538540840149},{"id":"https://openalex.org/keywords/satisfiability","display_name":"Satisfiability","score":0.4424040615558624},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.32538825273513794},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.21464109420776367},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.19474667310714722},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.1365135908126831},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.10297033190727234}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8289110660552979},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.5379323363304138},{"id":"https://openalex.org/C49937458","wikidata":"https://www.wikidata.org/wiki/Q2599292","display_name":"Probabilistic logic","level":2,"score":0.5255288481712341},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.4965561032295227},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.48122334480285645},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.48012304306030273},{"id":"https://openalex.org/C124681953","wikidata":"https://www.wikidata.org/wiki/Q339062","display_name":"Decomposition","level":2,"score":0.4783334732055664},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.46144384145736694},{"id":"https://openalex.org/C115901376","wikidata":"https://www.wikidata.org/wiki/Q184199","display_name":"Automation","level":2,"score":0.4499538540840149},{"id":"https://openalex.org/C168773769","wikidata":"https://www.wikidata.org/wiki/Q1350299","display_name":"Satisfiability","level":2,"score":0.4424040615558624},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.32538825273513794},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.21464109420776367},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.19474667310714722},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.1365135908126831},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.10297033190727234},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C18903297","wikidata":"https://www.wikidata.org/wiki/Q7150","display_name":"Ecology","level":1,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/bf00134684","is_oa":false,"landing_page_url":"https://doi.org/10.1007/bf00134684","pdf_url":null,"source":{"id":"https://openalex.org/S85498321","display_name":"Design Automation for Embedded Systems","issn_l":"0929-5585","issn":["0929-5585","1572-8080"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Design Automation for Embedded Systems","raw_type":"journal-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4300000071525574,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":54,"referenced_works":["https://openalex.org/W6164475","https://openalex.org/W1485093219","https://openalex.org/W1495162277","https://openalex.org/W1548878244","https://openalex.org/W1555915743","https://openalex.org/W1575115198","https://openalex.org/W1595227826","https://openalex.org/W1875492031","https://openalex.org/W1910128372","https://openalex.org/W1937914841","https://openalex.org/W1978118906","https://openalex.org/W1979486932","https://openalex.org/W1984197882","https://openalex.org/W2004068104","https://openalex.org/W2004659537","https://openalex.org/W2010398371","https://openalex.org/W2011039300","https://openalex.org/W2015509025","https://openalex.org/W2034419863","https://openalex.org/W2038904603","https://openalex.org/W2042202727","https://openalex.org/W2052271830","https://openalex.org/W2054918342","https://openalex.org/W2098844138","https://openalex.org/W2102472587","https://openalex.org/W2108053312","https://openalex.org/W2113535112","https://openalex.org/W2114304170","https://openalex.org/W2123572303","https://openalex.org/W2125412556","https://openalex.org/W2126571018","https://openalex.org/W2131913479","https://openalex.org/W2132609395","https://openalex.org/W2135308029","https://openalex.org/W2146161295","https://openalex.org/W2161455936","https://openalex.org/W2161484642","https://openalex.org/W2163835031","https://openalex.org/W2169238357","https://openalex.org/W2335345028","https://openalex.org/W2503657378","https://openalex.org/W2504509476","https://openalex.org/W2534739497","https://openalex.org/W2548275329","https://openalex.org/W3112258640","https://openalex.org/W3119437944","https://openalex.org/W3150566124","https://openalex.org/W3158830358","https://openalex.org/W4206455946","https://openalex.org/W4237769480","https://openalex.org/W4239080626","https://openalex.org/W4245941610","https://openalex.org/W4249287040","https://openalex.org/W4253365336"],"related_works":["https://openalex.org/W3022794856","https://openalex.org/W4281926497","https://openalex.org/W2494523064","https://openalex.org/W2943623134","https://openalex.org/W2588219639","https://openalex.org/W2519676117","https://openalex.org/W2030292806","https://openalex.org/W2215759665","https://openalex.org/W2960358116","https://openalex.org/W3214257365"],"abstract_inverted_index":null,"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2015,"cited_by_count":1}],"updated_date":"2026-08-21T09:56:20.448147","created_date":"2025-10-10T00:00:00"}