{"id":"https://openalex.org/W612784192","doi":"https://doi.org/10.1007/b137645","title":"Statistical Analysis and Optimization for VLSI: Timing and Power","display_name":"Statistical Analysis and Optimization for VLSI: Timing and Power","publication_year":2005,"publication_date":"2005-01-01","ids":{"openalex":"https://openalex.org/W612784192","doi":"https://doi.org/10.1007/b137645","mag":"612784192"},"language":"en","primary_location":{"id":"doi:10.1007/b137645","is_oa":false,"landing_page_url":"http://doi.org/10.1007/b137645","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Series on Integrated Circuits and Systems","raw_type":"book"},"type":"book","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5104002990","display_name":"Ashish Srivastava","orcid":null},"institutions":[{"id":"https://openalex.org/I27837315","display_name":"University of Michigan","ror":"https://ror.org/00jmfr291","country_code":"US","type":"education","lineage":["https://openalex.org/I27837315"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Srivastava, Ashish","raw_affiliation_strings":["University of Michigan, Ann Abor"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Michigan, Ann Abor","institution_ids":["https://openalex.org/I27837315"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000767141","display_name":"Dennis Sylvester","orcid":"https://orcid.org/0000-0003-2598-0458"},"institutions":[{"id":"https://openalex.org/I27837315","display_name":"University of Michigan","ror":"https://ror.org/00jmfr291","country_code":"US","type":"education","lineage":["https://openalex.org/I27837315"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sylvester, Dennis","raw_affiliation_strings":["University of Michigan, Ann Abor"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Michigan, Ann Abor","institution_ids":["https://openalex.org/I27837315"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5026311377","display_name":"David Blaauw","orcid":"https://orcid.org/0000-0001-6744-7075"},"institutions":[{"id":"https://openalex.org/I27837315","display_name":"University of Michigan","ror":"https://ror.org/00jmfr291","country_code":"US","type":"education","lineage":["https://openalex.org/I27837315"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Blaauw, David","raw_affiliation_strings":["University of Michigan, Ann Abor"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Michigan, Ann Abor","institution_ids":["https://openalex.org/I27837315"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":13.4135,"has_fulltext":false,"cited_by_count":263,"citation_normalized_percentile":{"value":0.9954955,"is_in_top_1_percent":true,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":100},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9897000193595886,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9897000193595886,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9865000247955322,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9807999730110168,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.7742226719856262},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5859590768814087},{"id":"https://openalex.org/keywords/power-analysis","display_name":"Power analysis","score":0.47317010164260864},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.4557291269302368},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4404156804084778},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3391384184360504},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.33208003640174866},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.21848025918006897},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.15850070118904114},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.05583393573760986}],"concepts":[{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.7742226719856262},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5859590768814087},{"id":"https://openalex.org/C71743495","wikidata":"https://www.wikidata.org/wiki/Q2845210","display_name":"Power analysis","level":3,"score":0.47317010164260864},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.4557291269302368},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4404156804084778},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3391384184360504},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.33208003640174866},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.21848025918006897},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.15850070118904114},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.05583393573760986},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C178489894","wikidata":"https://www.wikidata.org/wiki/Q8789","display_name":"Cryptography","level":2,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1007/b137645","is_oa":false,"landing_page_url":"http://doi.org/10.1007/b137645","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Series on Integrated Circuits and Systems","raw_type":"book"},{"id":"pmh:oai:aleph.bib-bvb.de:BVB01-016319831","is_oa":false,"landing_page_url":"https://doi.org/10.1007/b137645","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"software, multimedia"},{"id":"pmh:oai:dial.uclouvain.be:ebook:520","is_oa":false,"landing_page_url":"http://hdl.handle.net/2078/ebook:520","pdf_url":null,"source":{"id":"https://openalex.org/S4306401902","display_name":"Digital Access to Libraries (Universit\u00e9 catholique de Louvain (UCL), l'Universit\u00e9 de Namur (UNamur) and the Universit\u00e9 Saint-Louis (USL-B))","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I95674353","host_organization_name":"UCLouvain","host_organization_lineage":["https://openalex.org/I95674353"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":""}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W1997145140","https://openalex.org/W4236512364","https://openalex.org/W2034384303","https://openalex.org/W2046094129","https://openalex.org/W4252688335","https://openalex.org/W1933802032","https://openalex.org/W196104695","https://openalex.org/W2074088899","https://openalex.org/W2037668345","https://openalex.org/W1561552270"],"abstract_inverted_index":null,"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":3},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":5},{"year":2020,"cited_by_count":8},{"year":2019,"cited_by_count":7},{"year":2018,"cited_by_count":11},{"year":2017,"cited_by_count":7},{"year":2016,"cited_by_count":9},{"year":2015,"cited_by_count":7},{"year":2014,"cited_by_count":12},{"year":2013,"cited_by_count":16},{"year":2012,"cited_by_count":19}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2016-06-24T00:00:00"}
