{"id":"https://openalex.org/W2967373061","doi":"https://doi.org/10.1007/978-981-32-9767-8_53","title":"Low Leakage Highly Stable Robust Ultra Low Power 8T SRAM Cell","display_name":"Low Leakage Highly Stable Robust Ultra Low Power 8T SRAM Cell","publication_year":2019,"publication_date":"2019-01-01","ids":{"openalex":"https://openalex.org/W2967373061","doi":"https://doi.org/10.1007/978-981-32-9767-8_53","mag":"2967373061"},"language":"en","primary_location":{"id":"doi:10.1007/978-981-32-9767-8_53","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-981-32-9767-8_53","pdf_url":null,"source":{"id":"https://openalex.org/S2764900261","display_name":"Communications in computer and information science","issn_l":"1865-0929","issn":["1865-0929","1865-0937"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Communications in Computer and Information Science","raw_type":"book-chapter"},"type":"book-chapter","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101863165","display_name":"Neha Gupta","orcid":"https://orcid.org/0000-0003-2239-535X"},"institutions":[{"id":"https://openalex.org/I64295750","display_name":"Indian Institute of Technology Indore","ror":"https://ror.org/01hhf7w52","country_code":"IN","type":"education","lineage":["https://openalex.org/I64295750"]}],"countries":["IN"],"is_corresponding":true,"raw_author_name":"Neha Gupta","raw_affiliation_strings":["Nanoscale Devices, VLSI Circuit and System Design Lab, Discipline of Electrical Engineering, Indian Institute of Technology Indore, Indore, 453552, M.P., India"],"affiliations":[{"raw_affiliation_string":"Nanoscale Devices, VLSI Circuit and System Design Lab, Discipline of Electrical Engineering, Indian Institute of Technology Indore, Indore, 453552, M.P., India","institution_ids":["https://openalex.org/I64295750"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108265203","display_name":"Tanisha Gupta","orcid":null},"institutions":[{"id":"https://openalex.org/I138272832","display_name":"Devi Ahilya Vishwavidyalaya","ror":"https://ror.org/05c2p1f98","country_code":"IN","type":"education","lineage":["https://openalex.org/I138272832"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Tanisha Gupta","raw_affiliation_strings":["School of Electronics, Devi Ahilya Vishwavidyalaya, Indore, 452001, M.P., India"],"affiliations":[{"raw_affiliation_string":"School of Electronics, Devi Ahilya Vishwavidyalaya, Indore, 452001, M.P., India","institution_ids":["https://openalex.org/I138272832"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034456662","display_name":"Sajid Khan","orcid":"https://orcid.org/0000-0002-3724-9251"},"institutions":[{"id":"https://openalex.org/I64295750","display_name":"Indian Institute of Technology Indore","ror":"https://ror.org/01hhf7w52","country_code":"IN","type":"education","lineage":["https://openalex.org/I64295750"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Sajid Khan","raw_affiliation_strings":["Nanoscale Devices, VLSI Circuit and System Design Lab, Discipline of Electrical Engineering, Indian Institute of Technology Indore, Indore, 453552, M.P., India"],"affiliations":[{"raw_affiliation_string":"Nanoscale Devices, VLSI Circuit and System Design Lab, Discipline of Electrical Engineering, Indian Institute of Technology Indore, Indore, 453552, M.P., India","institution_ids":["https://openalex.org/I64295750"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071946179","display_name":"Abhinav Vishwakarma","orcid":null},"institutions":[{"id":"https://openalex.org/I64295750","display_name":"Indian Institute of Technology Indore","ror":"https://ror.org/01hhf7w52","country_code":"IN","type":"education","lineage":["https://openalex.org/I64295750"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Abhinav Vishwakarma","raw_affiliation_strings":["Nanoscale Devices, VLSI Circuit and System Design Lab, Discipline of Electrical Engineering, Indian Institute of Technology Indore, Indore, 453552, M.P., India"],"affiliations":[{"raw_affiliation_string":"Nanoscale Devices, VLSI Circuit and System Design Lab, Discipline of Electrical Engineering, Indian Institute of Technology Indore, Indore, 453552, M.P., India","institution_ids":["https://openalex.org/I64295750"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5068792760","display_name":"Santosh Kumar Vishvakarma","orcid":"https://orcid.org/0000-0003-4223-0077"},"institutions":[{"id":"https://openalex.org/I64295750","display_name":"Indian Institute of Technology Indore","ror":"https://ror.org/01hhf7w52","country_code":"IN","type":"education","lineage":["https://openalex.org/I64295750"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Santosh Kumar Vishvakarma","raw_affiliation_strings":["Electrical Engineering, Indian Institute of Technology Indore, Indore, India","Nanoscale Devices, VLSI Circuit and System Design Lab, Discipline of Electrical Engineering, Indian Institute of Technology Indore, Indore, 453552, M.P., India"],"affiliations":[{"raw_affiliation_string":"Electrical Engineering, Indian Institute of Technology Indore, Indore, India","institution_ids":["https://openalex.org/I64295750"]},{"raw_affiliation_string":"Nanoscale Devices, VLSI Circuit and System Design Lab, Discipline of Electrical Engineering, Indian Institute of Technology Indore, Indore, 453552, M.P., India","institution_ids":["https://openalex.org/I64295750"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5101863165"],"corresponding_institution_ids":["https://openalex.org/I64295750"],"apc_list":null,"apc_paid":null,"fwci":0.7443,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.68109584,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"643","last_page":"654"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/leakage","display_name":"Leakage (economics)","score":0.7495792508125305},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.6682532429695129},{"id":"https://openalex.org/keywords/leakage-power","display_name":"Leakage power","score":0.6470392942428589},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.6159768104553223},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5736263990402222},{"id":"https://openalex.org/keywords/ultra-low-power","display_name":"Ultra low power","score":0.5719958543777466},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5690202713012695},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.5289646983146667},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.503635823726654},{"id":"https://openalex.org/keywords/memory-cell","display_name":"Memory cell","score":0.4453738331794739},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3941299021244049},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3782937824726105},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.22645634412765503},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.16930702328681946},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1507856249809265},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.1274365484714508}],"concepts":[{"id":"https://openalex.org/C2777042071","wikidata":"https://www.wikidata.org/wiki/Q6509304","display_name":"Leakage (economics)","level":2,"score":0.7495792508125305},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.6682532429695129},{"id":"https://openalex.org/C2987719587","wikidata":"https://www.wikidata.org/wiki/Q1811428","display_name":"Leakage power","level":4,"score":0.6470392942428589},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.6159768104553223},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5736263990402222},{"id":"https://openalex.org/C3017773396","wikidata":"https://www.wikidata.org/wiki/Q6692774","display_name":"Ultra low power","level":4,"score":0.5719958543777466},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5690202713012695},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.5289646983146667},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.503635823726654},{"id":"https://openalex.org/C2776638159","wikidata":"https://www.wikidata.org/wiki/Q18343761","display_name":"Memory cell","level":4,"score":0.4453738331794739},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3941299021244049},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3782937824726105},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.22645634412765503},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.16930702328681946},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1507856249809265},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.1274365484714508},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/978-981-32-9767-8_53","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-981-32-9767-8_53","pdf_url":null,"source":{"id":"https://openalex.org/S2764900261","display_name":"Communications in computer and information science","issn_l":"1865-0929","issn":["1865-0929","1865-0937"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Communications in Computer and Information Science","raw_type":"book-chapter"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8700000047683716,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W274004780","https://openalex.org/W1753784006","https://openalex.org/W1974159394","https://openalex.org/W2002612140","https://openalex.org/W2035589388","https://openalex.org/W2113362353","https://openalex.org/W2122497527","https://openalex.org/W2131833150","https://openalex.org/W2157743350","https://openalex.org/W2496254462","https://openalex.org/W2793929663","https://openalex.org/W2794453321","https://openalex.org/W2804691385","https://openalex.org/W2886085896","https://openalex.org/W2889235776","https://openalex.org/W6637817741"],"related_works":["https://openalex.org/W2297319780","https://openalex.org/W2178217057","https://openalex.org/W1972800815","https://openalex.org/W2548830639","https://openalex.org/W2159770326","https://openalex.org/W4252086734","https://openalex.org/W1505038800","https://openalex.org/W2051027227","https://openalex.org/W2953793304","https://openalex.org/W4301258909"],"abstract_inverted_index":null,"counts_by_year":[{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
