{"id":"https://openalex.org/W2782503170","doi":"https://doi.org/10.1007/978-981-10-7844-6_12","title":"Research of Configurable Hybrid Memory Architecture for Big Data Processing","display_name":"Research of Configurable Hybrid Memory Architecture for Big Data Processing","publication_year":2018,"publication_date":"2018-01-01","ids":{"openalex":"https://openalex.org/W2782503170","doi":"https://doi.org/10.1007/978-981-10-7844-6_12","mag":"2782503170"},"language":"en","primary_location":{"id":"doi:10.1007/978-981-10-7844-6_12","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-981-10-7844-6_12","pdf_url":null,"source":{"id":"https://openalex.org/S2764900261","display_name":"Communications in computer and information science","issn_l":"1865-0929","issn":["1865-0929","1865-0937"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Communications in Computer and Information Science","raw_type":"book-chapter"},"type":"book-chapter","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5010062994","display_name":"Hongwei Zhou","orcid":"https://orcid.org/0009-0002-9782-9415"},"institutions":[{"id":"https://openalex.org/I170215575","display_name":"National University of Defense Technology","ror":"https://ror.org/05d2yfz11","country_code":"CN","type":"education","lineage":["https://openalex.org/I170215575"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Hongwei Zhou","raw_affiliation_strings":["College of Computer, National University of Defense Technology, Changsha, 410073, China"],"affiliations":[{"raw_affiliation_string":"College of Computer, National University of Defense Technology, Changsha, 410073, China","institution_ids":["https://openalex.org/I170215575"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019904497","display_name":"Rangyu Deng","orcid":null},"institutions":[{"id":"https://openalex.org/I170215575","display_name":"National University of Defense Technology","ror":"https://ror.org/05d2yfz11","country_code":"CN","type":"education","lineage":["https://openalex.org/I170215575"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Rangyu Deng","raw_affiliation_strings":["College of Computer, National University of Defense Technology, Changsha, 410073, China"],"affiliations":[{"raw_affiliation_string":"College of Computer, National University of Defense Technology, Changsha, 410073, China","institution_ids":["https://openalex.org/I170215575"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100517886","display_name":"Quanyou Feng","orcid":null},"institutions":[{"id":"https://openalex.org/I170215575","display_name":"National University of Defense Technology","ror":"https://ror.org/05d2yfz11","country_code":"CN","type":"education","lineage":["https://openalex.org/I170215575"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Quanyou Feng","raw_affiliation_strings":["College of Computer, National University of Defense Technology, Changsha, 410073, China"],"affiliations":[{"raw_affiliation_string":"College of Computer, National University of Defense Technology, Changsha, 410073, China","institution_ids":["https://openalex.org/I170215575"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5038440892","display_name":"Xiaoqiang Ni","orcid":null},"institutions":[{"id":"https://openalex.org/I170215575","display_name":"National University of Defense Technology","ror":"https://ror.org/05d2yfz11","country_code":"CN","type":"education","lineage":["https://openalex.org/I170215575"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaoqiang Ni","raw_affiliation_strings":["College of Computer, National University of Defense Technology, Changsha, 410073, China"],"affiliations":[{"raw_affiliation_string":"College of Computer, National University of Defense Technology, Changsha, 410073, China","institution_ids":["https://openalex.org/I170215575"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5103276566","display_name":"Qiang Dou","orcid":"https://orcid.org/0000-0003-2320-8413"},"institutions":[{"id":"https://openalex.org/I170215575","display_name":"National University of Defense Technology","ror":"https://ror.org/05d2yfz11","country_code":"CN","type":"education","lineage":["https://openalex.org/I170215575"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Qiang Dou","raw_affiliation_strings":["College of Computer, National University of Defense Technology, Changsha, 410073, China"],"affiliations":[{"raw_affiliation_string":"College of Computer, National University of Defense Technology, Changsha, 410073, China","institution_ids":["https://openalex.org/I170215575"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5010062994"],"corresponding_institution_ids":["https://openalex.org/I170215575"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.02549575,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"116","last_page":"132"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9926999807357788,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9921000003814697,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8361748456954956},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.7527188062667847},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.7377257943153381},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.700069785118103},{"id":"https://openalex.org/keywords/flat-memory-model","display_name":"Flat memory model","score":0.6483721733093262},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.6299309134483337},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.6069555878639221},{"id":"https://openalex.org/keywords/cache-only-memory-architecture","display_name":"Cache-only memory architecture","score":0.6031477451324463},{"id":"https://openalex.org/keywords/non-uniform-memory-access","display_name":"Non-uniform memory access","score":0.572735607624054},{"id":"https://openalex.org/keywords/extended-memory","display_name":"Extended memory","score":0.562570333480835},{"id":"https://openalex.org/keywords/computing-with-memory","display_name":"Computing with Memory","score":0.5314326286315918},{"id":"https://openalex.org/keywords/memory-map","display_name":"Memory map","score":0.5097360014915466},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4990510940551758},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.489360511302948},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.486578106880188},{"id":"https://openalex.org/keywords/physical-address","display_name":"Physical address","score":0.481748104095459},{"id":"https://openalex.org/keywords/distributed-shared-memory","display_name":"Distributed shared memory","score":0.43841981887817383},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.42613619565963745},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.42370694875717163},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.40784162282943726},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.35120177268981934}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8361748456954956},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.7527188062667847},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.7377257943153381},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.700069785118103},{"id":"https://openalex.org/C57863822","wikidata":"https://www.wikidata.org/wiki/Q905488","display_name":"Flat memory model","level":4,"score":0.6483721733093262},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.6299309134483337},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.6069555878639221},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.6031477451324463},{"id":"https://openalex.org/C133371097","wikidata":"https://www.wikidata.org/wiki/Q868014","display_name":"Non-uniform memory access","level":5,"score":0.572735607624054},{"id":"https://openalex.org/C171675096","wikidata":"https://www.wikidata.org/wiki/Q1143380","display_name":"Extended memory","level":4,"score":0.562570333480835},{"id":"https://openalex.org/C152890283","wikidata":"https://www.wikidata.org/wiki/Q4129922","display_name":"Computing with Memory","level":5,"score":0.5314326286315918},{"id":"https://openalex.org/C74426580","wikidata":"https://www.wikidata.org/wiki/Q719484","display_name":"Memory map","level":3,"score":0.5097360014915466},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4990510940551758},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.489360511302948},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.486578106880188},{"id":"https://openalex.org/C41036726","wikidata":"https://www.wikidata.org/wiki/Q844824","display_name":"Physical address","level":3,"score":0.481748104095459},{"id":"https://openalex.org/C39528615","wikidata":"https://www.wikidata.org/wiki/Q1229610","display_name":"Distributed shared memory","level":5,"score":0.43841981887817383},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.42613619565963745},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.42370694875717163},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.40784162282943726},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.35120177268981934}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/978-981-10-7844-6_12","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-981-10-7844-6_12","pdf_url":null,"source":{"id":"https://openalex.org/S2764900261","display_name":"Communications in computer and information science","issn_l":"1865-0929","issn":["1865-0929","1865-0937"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Communications in Computer and Information Science","raw_type":"book-chapter"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.7400000095367432,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W26183006","https://openalex.org/W1564523715","https://openalex.org/W1968686941","https://openalex.org/W1980364632","https://openalex.org/W1982398126","https://openalex.org/W1983826793","https://openalex.org/W2028802049","https://openalex.org/W2035156756","https://openalex.org/W2043340768","https://openalex.org/W2060254132","https://openalex.org/W2069367007","https://openalex.org/W2071208495","https://openalex.org/W2084007230","https://openalex.org/W2105271931","https://openalex.org/W2105408739","https://openalex.org/W2112261349","https://openalex.org/W2114429886","https://openalex.org/W2116826022","https://openalex.org/W2135393827","https://openalex.org/W2156159026","https://openalex.org/W2168972302","https://openalex.org/W2999811406","https://openalex.org/W4231378725","https://openalex.org/W4254177552"],"related_works":["https://openalex.org/W2168550483","https://openalex.org/W2565280077","https://openalex.org/W2782503170","https://openalex.org/W4243576563","https://openalex.org/W4321458411","https://openalex.org/W2316890442","https://openalex.org/W4281924108","https://openalex.org/W2047684617","https://openalex.org/W2145484885","https://openalex.org/W2041174925"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
