{"id":"https://openalex.org/W1829177146","doi":"https://doi.org/10.1007/978-90-481-3660-5_55","title":"Encapsulating connections on SoC designs using ASM++ charts","display_name":"Encapsulating connections on SoC designs using ASM++ charts","publication_year":2009,"publication_date":"2009-12-15","ids":{"openalex":"https://openalex.org/W1829177146","doi":"https://doi.org/10.1007/978-90-481-3660-5_55","mag":"1829177146"},"language":"en","primary_location":{"id":"doi:10.1007/978-90-481-3660-5_55","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-90-481-3660-5_55","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Advanced Techniques in Computing Sciences and Software Engineering","raw_type":"book-chapter"},"type":"book-chapter","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5066434247","display_name":"Santiago de Pablo","orcid":"https://orcid.org/0000-0001-6932-1476"},"institutions":[{"id":"https://openalex.org/I108103353","display_name":"Universidad de Valladolid","ror":"https://ror.org/01fvbaw18","country_code":"ES","type":"education","lineage":["https://openalex.org/I108103353"]}],"countries":["ES"],"is_corresponding":true,"raw_author_name":"Santiago de Pablo","raw_affiliation_strings":["University of Valladolid, Valladolid, Spain"],"affiliations":[{"raw_affiliation_string":"University of Valladolid, Valladolid, Spain","institution_ids":["https://openalex.org/I108103353"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5064143059","display_name":"Luis C. Herrero","orcid":"https://orcid.org/0000-0002-2631-5962"},"institutions":[{"id":"https://openalex.org/I108103353","display_name":"Universidad de Valladolid","ror":"https://ror.org/01fvbaw18","country_code":"ES","type":"education","lineage":["https://openalex.org/I108103353"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Luis C. Herrero","raw_affiliation_strings":["University of Valladolid, Valladolid, Spain"],"affiliations":[{"raw_affiliation_string":"University of Valladolid, Valladolid, Spain","institution_ids":["https://openalex.org/I108103353"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070355105","display_name":"Fernando Martinez\u2010Rodrigo","orcid":"https://orcid.org/0000-0002-0508-4106"},"institutions":[{"id":"https://openalex.org/I108103353","display_name":"Universidad de Valladolid","ror":"https://ror.org/01fvbaw18","country_code":"ES","type":"education","lineage":["https://openalex.org/I108103353"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Fernando Mart\u00ednez","raw_affiliation_strings":["University of Valladolid, Valladolid, Spain"],"affiliations":[{"raw_affiliation_string":"University of Valladolid, Valladolid, Spain","institution_ids":["https://openalex.org/I108103353"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5026960669","display_name":"Alexis B. Rey\u2010Bou\u00e9","orcid":"https://orcid.org/0000-0002-9004-8651"},"institutions":[{"id":"https://openalex.org/I3123212020","display_name":"Universidad Polit\u00e9cnica de Cartagena","ror":"https://ror.org/02k5kx966","country_code":"ES","type":"education","lineage":["https://openalex.org/I3123212020"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"Alexis B. Rey","raw_affiliation_strings":["Technical University of Cartagena, Cartagena, Murcia, Spain"],"affiliations":[{"raw_affiliation_string":"Technical University of Cartagena, Cartagena, Murcia, Spain","institution_ids":["https://openalex.org/I3123212020"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5066434247"],"corresponding_institution_ids":["https://openalex.org/I108103353"],"apc_list":null,"apc_paid":null,"fwci":0.4114,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.67623318,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"323","last_page":"328"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.8572047352790833},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8134516477584839},{"id":"https://openalex.org/keywords/parameterized-complexity","display_name":"Parameterized complexity","score":0.6898635029792786},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.614430844783783},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.5024518966674805},{"id":"https://openalex.org/keywords/simple","display_name":"Simple (philosophy)","score":0.4888107478618622},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.4743717312812805},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.41498127579689026},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3934473991394043},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.34834134578704834},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.15184640884399414},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1304582953453064}],"concepts":[{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.8572047352790833},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8134516477584839},{"id":"https://openalex.org/C165464430","wikidata":"https://www.wikidata.org/wiki/Q1570441","display_name":"Parameterized complexity","level":2,"score":0.6898635029792786},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.614430844783783},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.5024518966674805},{"id":"https://openalex.org/C2780586882","wikidata":"https://www.wikidata.org/wiki/Q7520643","display_name":"Simple (philosophy)","level":2,"score":0.4888107478618622},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.4743717312812805},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.41498127579689026},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3934473991394043},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.34834134578704834},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.15184640884399414},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1304582953453064},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/978-90-481-3660-5_55","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-90-481-3660-5_55","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Advanced Techniques in Computing Sciences and Software Engineering","raw_type":"book-chapter"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1500142795","https://openalex.org/W1506034564","https://openalex.org/W1608459562","https://openalex.org/W1842313047","https://openalex.org/W2049443371","https://openalex.org/W2097670457","https://openalex.org/W2120277802","https://openalex.org/W2164587072","https://openalex.org/W4232808664","https://openalex.org/W4236334728"],"related_works":["https://openalex.org/W2051058708","https://openalex.org/W154868527","https://openalex.org/W1494268238","https://openalex.org/W1983207144","https://openalex.org/W2490706771","https://openalex.org/W78782492","https://openalex.org/W2122949436","https://openalex.org/W1043594576","https://openalex.org/W190963477","https://openalex.org/W2077870657"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2026-04-23T09:07:50.710637","created_date":"2025-10-10T00:00:00"}
