{"id":"https://openalex.org/W1773595569","doi":"https://doi.org/10.1007/978-3-642-84304-4_3","title":"HIPARE: Hierarchical Circuit and Parameter Extraction from Mask Layout Data","display_name":"HIPARE: Hierarchical Circuit and Parameter Extraction from Mask Layout Data","publication_year":1990,"publication_date":"1990-01-01","ids":{"openalex":"https://openalex.org/W1773595569","doi":"https://doi.org/10.1007/978-3-642-84304-4_3","mag":"1773595569"},"language":"de","primary_location":{"id":"doi:10.1007/978-3-642-84304-4_3","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-642-84304-4_3","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Rechnergest\u00fctzter Entwurf und Architektur mikroelektronischer Systeme","raw_type":"book-chapter"},"type":"book-chapter","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5071062984","display_name":"U. R\u00f6ttcher","orcid":null},"institutions":[{"id":"https://openalex.org/I4210100127","display_name":"Fraunhofer Institute for Microelectronic Circuits and Systems","ror":"https://ror.org/01243c877","country_code":"DE","type":"facility","lineage":["https://openalex.org/I4210100127","https://openalex.org/I4923324"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"U. R\u00f6ttcher","raw_affiliation_strings":["Fraunhofer Institute of Microelectronic Circuits and Systems, Finkenstr. 61, D-4100, Duisburg 1, Germany"],"affiliations":[{"raw_affiliation_string":"Fraunhofer Institute of Microelectronic Circuits and Systems, Finkenstr. 61, D-4100, Duisburg 1, Germany","institution_ids":["https://openalex.org/I4210100127"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5054672567","display_name":"J. Fritz","orcid":null},"institutions":[{"id":"https://openalex.org/I4210100127","display_name":"Fraunhofer Institute for Microelectronic Circuits and Systems","ror":"https://ror.org/01243c877","country_code":"DE","type":"facility","lineage":["https://openalex.org/I4210100127","https://openalex.org/I4923324"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"J. Fritz","raw_affiliation_strings":["Fraunhofer Institute of Microelectronic Circuits and Systems, Finkenstr. 61, D-4100, Duisburg 1, Germany"],"affiliations":[{"raw_affiliation_string":"Fraunhofer Institute of Microelectronic Circuits and Systems, Finkenstr. 61, D-4100, Duisburg 1, Germany","institution_ids":["https://openalex.org/I4210100127"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069908329","display_name":"F. Krohm","orcid":null},"institutions":[{"id":"https://openalex.org/I4210100127","display_name":"Fraunhofer Institute for Microelectronic Circuits and Systems","ror":"https://ror.org/01243c877","country_code":"DE","type":"facility","lineage":["https://openalex.org/I4210100127","https://openalex.org/I4923324"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"F. Krohm","raw_affiliation_strings":["Fraunhofer Institute of Microelectronic Circuits and Systems, Finkenstr. 61, D-4100, Duisburg 1, Germany"],"affiliations":[{"raw_affiliation_string":"Fraunhofer Institute of Microelectronic Circuits and Systems, Finkenstr. 61, D-4100, Duisburg 1, Germany","institution_ids":["https://openalex.org/I4210100127"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5019127779","display_name":"Gunther Hess","orcid":null},"institutions":[{"id":"https://openalex.org/I4210100127","display_name":"Fraunhofer Institute for Microelectronic Circuits and Systems","ror":"https://ror.org/01243c877","country_code":"DE","type":"facility","lineage":["https://openalex.org/I4210100127","https://openalex.org/I4923324"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"G. Hess","raw_affiliation_strings":["Fraunhofer Institute of Microelectronic Circuits and Systems, Finkenstr. 61, D-4100, Duisburg 1, Germany"],"affiliations":[{"raw_affiliation_string":"Fraunhofer Institute of Microelectronic Circuits and Systems, Finkenstr. 61, D-4100, Duisburg 1, Germany","institution_ids":["https://openalex.org/I4210100127"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5071062984"],"corresponding_institution_ids":["https://openalex.org/I4210100127"],"apc_list":null,"apc_paid":null,"fwci":1.8658,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.86367969,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"24","last_page":"32"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9973999857902527,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12784","display_name":"Modular Robots and Swarm Intelligence","score":0.9958000183105469,"subfield":{"id":"https://openalex.org/subfields/2210","display_name":"Mechanical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/parasitic-extraction","display_name":"Parasitic extraction","score":0.8957623243331909},{"id":"https://openalex.org/keywords/modularity","display_name":"Modularity (biology)","score":0.795332133769989},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.683060348033905},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.5445071458816528},{"id":"https://openalex.org/keywords/hierarchical-database-model","display_name":"Hierarchical database model","score":0.502554178237915},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.44634199142456055},{"id":"https://openalex.org/keywords/circuit-extraction","display_name":"Circuit extraction","score":0.43760403990745544},{"id":"https://openalex.org/keywords/ic-layout-editor","display_name":"IC layout editor","score":0.4238697290420532},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.37564340233802795},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.3460594415664673},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3346092104911804},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.30667752027511597},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.2900913655757904},{"id":"https://openalex.org/keywords/equivalent-circuit","display_name":"Equivalent circuit","score":0.2714870572090149},{"id":"https://openalex.org/keywords/data-mining","display_name":"Data mining","score":0.26217901706695557},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2014237940311432},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1769348680973053},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.09337431192398071}],"concepts":[{"id":"https://openalex.org/C159818811","wikidata":"https://www.wikidata.org/wiki/Q7135947","display_name":"Parasitic extraction","level":2,"score":0.8957623243331909},{"id":"https://openalex.org/C2779478453","wikidata":"https://www.wikidata.org/wiki/Q6889748","display_name":"Modularity (biology)","level":2,"score":0.795332133769989},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.683060348033905},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.5445071458816528},{"id":"https://openalex.org/C144986985","wikidata":"https://www.wikidata.org/wiki/Q871236","display_name":"Hierarchical database model","level":2,"score":0.502554178237915},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.44634199142456055},{"id":"https://openalex.org/C26490066","wikidata":"https://www.wikidata.org/wiki/Q17006835","display_name":"Circuit extraction","level":4,"score":0.43760403990745544},{"id":"https://openalex.org/C5546195","wikidata":"https://www.wikidata.org/wiki/Q5969842","display_name":"IC layout editor","level":5,"score":0.4238697290420532},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.37564340233802795},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.3460594415664673},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3346092104911804},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.30667752027511597},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.2900913655757904},{"id":"https://openalex.org/C23572009","wikidata":"https://www.wikidata.org/wiki/Q964981","display_name":"Equivalent circuit","level":3,"score":0.2714870572090149},{"id":"https://openalex.org/C124101348","wikidata":"https://www.wikidata.org/wiki/Q172491","display_name":"Data mining","level":1,"score":0.26217901706695557},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2014237940311432},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1769348680973053},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.09337431192398071},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C54355233","wikidata":"https://www.wikidata.org/wiki/Q7162","display_name":"Genetics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/978-3-642-84304-4_3","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-642-84304-4_3","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Rechnergest\u00fctzter Entwurf und Architektur mikroelektronischer Systeme","raw_type":"book-chapter"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1650804443","https://openalex.org/W1874694348","https://openalex.org/W2011038129","https://openalex.org/W2053072356","https://openalex.org/W2066843548","https://openalex.org/W2084939417","https://openalex.org/W2116364098","https://openalex.org/W2139002947","https://openalex.org/W2144054006","https://openalex.org/W2151612684","https://openalex.org/W2158574829","https://openalex.org/W2159567219","https://openalex.org/W4210463919","https://openalex.org/W4232782792","https://openalex.org/W4240128100","https://openalex.org/W4243598588","https://openalex.org/W4245062236","https://openalex.org/W4246262701","https://openalex.org/W4247274432","https://openalex.org/W6652965007"],"related_works":["https://openalex.org/W2091329789","https://openalex.org/W1605062719","https://openalex.org/W85694287","https://openalex.org/W4239381562","https://openalex.org/W2131154858","https://openalex.org/W1565715208","https://openalex.org/W2143930978","https://openalex.org/W2376028644","https://openalex.org/W4253917875","https://openalex.org/W48176555"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}