{"id":"https://openalex.org/W1643784671","doi":"https://doi.org/10.1007/978-3-642-76930-6_29","title":"The Interlocking Bus Network For Fault-Tolerant Processor Arrays","display_name":"The Interlocking Bus Network For Fault-Tolerant Processor Arrays","publication_year":1991,"publication_date":"1991-01-01","ids":{"openalex":"https://openalex.org/W1643784671","doi":"https://doi.org/10.1007/978-3-642-76930-6_29","mag":"1643784671"},"language":"en","primary_location":{"id":"doi:10.1007/978-3-642-76930-6_29","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-642-76930-6_29","pdf_url":null,"source":{"id":"https://openalex.org/S4210212548","display_name":"Informatik-Fachberichte","issn_l":"0343-3005","issn":["0343-3005"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/P4310319965","host_organization_name":"Springer Nature","host_organization_lineage":["https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Informatik-Fachberichte","raw_type":"book-chapter"},"type":"book-chapter","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5048017742","display_name":"Markus Siegle","orcid":"https://orcid.org/0000-0001-7639-2280"},"institutions":[{"id":"https://openalex.org/I181369854","display_name":"Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg","ror":"https://ror.org/00f7hpc57","country_code":"DE","type":"education","lineage":["https://openalex.org/I181369854"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Markus G. Siegle","raw_affiliation_strings":["Institut f\u00fcr Informatik VII, Universit\u00e4t Erlangen, Martensstr.3, 8520, Erlangen, Germany"],"affiliations":[{"raw_affiliation_string":"Institut f\u00fcr Informatik VII, Universit\u00e4t Erlangen, Martensstr.3, 8520, Erlangen, Germany","institution_ids":["https://openalex.org/I181369854"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5030462464","display_name":"Douglas S. Reeves","orcid":"https://orcid.org/0000-0002-1775-0639"},"institutions":[{"id":"https://openalex.org/I137902535","display_name":"North Carolina State University","ror":"https://ror.org/04tj63d06","country_code":"US","type":"education","lineage":["https://openalex.org/I137902535"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Douglas S. Reeves","raw_affiliation_strings":["Department of Computer Science, North Carolina State University, Raleigh, NC, 27965, USA"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science, North Carolina State University, Raleigh, NC, 27965, USA","institution_ids":["https://openalex.org/I137902535"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5073020485","display_name":"Krzysztof Ko\u017ami\u0144ski","orcid":null},"institutions":[{"id":"https://openalex.org/I4210133640","display_name":"MCNC Research and Development Institute","ror":"https://ror.org/042awg277","country_code":"US","type":"facility","lineage":["https://openalex.org/I4210133640"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Krzysztof Kozminski","raw_affiliation_strings":["MCNC Center for Microelectronics, Research Triangle Park, NC, 27709, USA"],"affiliations":[{"raw_affiliation_string":"MCNC Center for Microelectronics, Research Triangle Park, NC, 27709, USA","institution_ids":["https://openalex.org/I4210133640"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5048017742"],"corresponding_institution_ids":["https://openalex.org/I181369854"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.25416945,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"348","last_page":"359"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9876999855041504,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/interlocking","display_name":"Interlocking","score":0.7606872320175171},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7016891241073608},{"id":"https://openalex.org/keywords/fault-tolerance","display_name":"Fault tolerance","score":0.5733810067176819},{"id":"https://openalex.org/keywords/local-bus","display_name":"Local bus","score":0.5661633014678955},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5559443235397339},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.5557761788368225},{"id":"https://openalex.org/keywords/bipartite-graph","display_name":"Bipartite graph","score":0.5354920029640198},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5155224800109863},{"id":"https://openalex.org/keywords/survivability","display_name":"Survivability","score":0.4910774230957031},{"id":"https://openalex.org/keywords/control-bus","display_name":"Control bus","score":0.4518513083457947},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.43086937069892883},{"id":"https://openalex.org/keywords/system-bus","display_name":"System bus","score":0.41750386357307434},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.3393709659576416},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.29350632429122925},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.29189741611480713},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.25525373220443726},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20062342286109924},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.11462241411209106},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.08147445321083069},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.07867717742919922}],"concepts":[{"id":"https://openalex.org/C2778844933","wikidata":"https://www.wikidata.org/wiki/Q630950","display_name":"Interlocking","level":2,"score":0.7606872320175171},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7016891241073608},{"id":"https://openalex.org/C63540848","wikidata":"https://www.wikidata.org/wiki/Q3140932","display_name":"Fault tolerance","level":2,"score":0.5733810067176819},{"id":"https://openalex.org/C202015219","wikidata":"https://www.wikidata.org/wiki/Q6664300","display_name":"Local bus","level":4,"score":0.5661633014678955},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5559443235397339},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5557761788368225},{"id":"https://openalex.org/C197657726","wikidata":"https://www.wikidata.org/wiki/Q174733","display_name":"Bipartite graph","level":3,"score":0.5354920029640198},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5155224800109863},{"id":"https://openalex.org/C2781133158","wikidata":"https://www.wikidata.org/wiki/Q1088669","display_name":"Survivability","level":2,"score":0.4910774230957031},{"id":"https://openalex.org/C203315745","wikidata":"https://www.wikidata.org/wiki/Q2235486","display_name":"Control bus","level":3,"score":0.4518513083457947},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.43086937069892883},{"id":"https://openalex.org/C136321198","wikidata":"https://www.wikidata.org/wiki/Q2377054","display_name":"System bus","level":2,"score":0.41750386357307434},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.3393709659576416},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.29350632429122925},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.29189741611480713},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.25525373220443726},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20062342286109924},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.11462241411209106},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.08147445321083069},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.07867717742919922}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1007/978-3-642-76930-6_29","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-642-76930-6_29","pdf_url":null,"source":{"id":"https://openalex.org/S4210212548","display_name":"Informatik-Fachberichte","issn_l":"0343-3005","issn":["0343-3005"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/P4310319965","host_organization_name":"Springer Nature","host_organization_lineage":["https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Informatik-Fachberichte","raw_type":"book-chapter"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.47.1586","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.47.1586","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"ftp://ftp.informatik.uni-erlangen.de/local/inf7/mmb/interlock.ps.Z","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W634100300","https://openalex.org/W1496170950","https://openalex.org/W1590529339","https://openalex.org/W2003588329","https://openalex.org/W2016889832","https://openalex.org/W2060937344","https://openalex.org/W2096046869","https://openalex.org/W2119241866","https://openalex.org/W2158365276","https://openalex.org/W2496556858","https://openalex.org/W2994762488","https://openalex.org/W6687380677"],"related_works":["https://openalex.org/W4255235451","https://openalex.org/W2387146226","https://openalex.org/W4244800129","https://openalex.org/W2787679733","https://openalex.org/W2404980846","https://openalex.org/W70103254","https://openalex.org/W2383984117","https://openalex.org/W1494565374","https://openalex.org/W2026314975","https://openalex.org/W2364771327"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}