{"id":"https://openalex.org/W266440567","doi":"https://doi.org/10.1007/978-3-642-54420-0_44","title":"A Novel Memory Subsystem and Computational Model for Parallel Reconfigurable Architectures","display_name":"A Novel Memory Subsystem and Computational Model for Parallel Reconfigurable Architectures","publication_year":2014,"publication_date":"2014-01-01","ids":{"openalex":"https://openalex.org/W266440567","doi":"https://doi.org/10.1007/978-3-642-54420-0_44","mag":"266440567"},"language":"en","primary_location":{"id":"doi:10.1007/978-3-642-54420-0_44","is_oa":true,"landing_page_url":"https://doi.org/10.1007/978-3-642-54420-0_44","pdf_url":"https://link.springer.com/content/pdf/10.1007%2F978-3-642-54420-0_44.pdf","source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},"type":"book-chapter","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"bronze","oa_url":"https://link.springer.com/content/pdf/10.1007%2F978-3-642-54420-0_44.pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5004731428","display_name":"Yamuna Rajasekhar","orcid":null},"institutions":[{"id":"https://openalex.org/I102149020","display_name":"University of North Carolina at Charlotte","ror":"https://ror.org/04dawnj30","country_code":"US","type":"education","lineage":["https://openalex.org/I102149020"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yamuna Rajasekhar","raw_affiliation_strings":["Reconfigurable Computing Systems Laboratory, University of North Carolina at Charlotte, USA","University of North Carolina at Charlotte*"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Reconfigurable Computing Systems Laboratory, University of North Carolina at Charlotte, USA","institution_ids":["https://openalex.org/I102149020"]},{"raw_affiliation_string":"University of North Carolina at Charlotte*","institution_ids":["https://openalex.org/I102149020"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5106082786","display_name":"Ron Sass","orcid":null},"institutions":[{"id":"https://openalex.org/I102149020","display_name":"University of North Carolina at Charlotte","ror":"https://ror.org/04dawnj30","country_code":"US","type":"education","lineage":["https://openalex.org/I102149020"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ron Sass","raw_affiliation_strings":["Reconfigurable Computing Systems Laboratory, University of North Carolina at Charlotte, USA","University of North Carolina at Charlotte*"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Reconfigurable Computing Systems Laboratory, University of North Carolina at Charlotte, USA","institution_ids":["https://openalex.org/I102149020"]},{"raw_affiliation_string":"University of North Carolina at Charlotte*","institution_ids":["https://openalex.org/I102149020"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":{"value":5000,"currency":"EUR","value_usd":5392},"apc_paid":null,"fwci":0.0,"has_fulltext":true,"cited_by_count":0,"citation_normalized_percentile":{"value":0.09606987,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"444","last_page":"453"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.785366415977478},{"id":"https://openalex.org/keywords/interleaved-memory","display_name":"Interleaved memory","score":0.6112380623817444},{"id":"https://openalex.org/keywords/registered-memory","display_name":"Registered memory","score":0.6005293130874634},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.5876526236534119},{"id":"https://openalex.org/keywords/memory-map","display_name":"Memory map","score":0.575373649597168},{"id":"https://openalex.org/keywords/computing-with-memory","display_name":"Computing with Memory","score":0.5497772693634033},{"id":"https://openalex.org/keywords/flat-memory-model","display_name":"Flat memory model","score":0.5288967490196228},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5188061594963074},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.5093652009963989},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.4979879856109619},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.4972594082355499},{"id":"https://openalex.org/keywords/cache-only-memory-architecture","display_name":"Cache-only memory architecture","score":0.46945875883102417},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.46674758195877075},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.43620991706848145},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.43519487977027893},{"id":"https://openalex.org/keywords/extended-memory","display_name":"Extended memory","score":0.43030282855033875},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.42715516686439514},{"id":"https://openalex.org/keywords/high-memory","display_name":"High memory","score":0.4253259599208832},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.3953053951263428},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3857390880584717},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.34377360343933105},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.33566659688949585},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.3261284828186035},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.26648664474487305}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.785366415977478},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.6112380623817444},{"id":"https://openalex.org/C93446704","wikidata":"https://www.wikidata.org/wiki/Q449328","display_name":"Registered memory","level":3,"score":0.6005293130874634},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.5876526236534119},{"id":"https://openalex.org/C74426580","wikidata":"https://www.wikidata.org/wiki/Q719484","display_name":"Memory map","level":3,"score":0.575373649597168},{"id":"https://openalex.org/C152890283","wikidata":"https://www.wikidata.org/wiki/Q4129922","display_name":"Computing with Memory","level":5,"score":0.5497772693634033},{"id":"https://openalex.org/C57863822","wikidata":"https://www.wikidata.org/wiki/Q905488","display_name":"Flat memory model","level":4,"score":0.5288967490196228},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5188061594963074},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.5093652009963989},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.4979879856109619},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.4972594082355499},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.46945875883102417},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.46674758195877075},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.43620991706848145},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.43519487977027893},{"id":"https://openalex.org/C171675096","wikidata":"https://www.wikidata.org/wiki/Q1143380","display_name":"Extended memory","level":4,"score":0.43030282855033875},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.42715516686439514},{"id":"https://openalex.org/C2781357197","wikidata":"https://www.wikidata.org/wiki/Q5757597","display_name":"High memory","level":2,"score":0.4253259599208832},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.3953053951263428},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3857390880584717},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.34377360343933105},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.33566659688949585},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.3261284828186035},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.26648664474487305},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/978-3-642-54420-0_44","is_oa":true,"landing_page_url":"https://doi.org/10.1007/978-3-642-54420-0_44","pdf_url":"https://link.springer.com/content/pdf/10.1007%2F978-3-642-54420-0_44.pdf","source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"}],"best_oa_location":{"id":"doi:10.1007/978-3-642-54420-0_44","is_oa":true,"landing_page_url":"https://doi.org/10.1007/978-3-642-54420-0_44","pdf_url":"https://link.springer.com/content/pdf/10.1007%2F978-3-642-54420-0_44.pdf","source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.5099999904632568,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W266440567.pdf","grobid_xml":"https://content.openalex.org/works/W266440567.grobid-xml"},"referenced_works_count":12,"referenced_works":["https://openalex.org/W1983096721","https://openalex.org/W2059024810","https://openalex.org/W2068343370","https://openalex.org/W2082754615","https://openalex.org/W2096070062","https://openalex.org/W2101308451","https://openalex.org/W2105323257","https://openalex.org/W2119543864","https://openalex.org/W2174102096","https://openalex.org/W2404298441","https://openalex.org/W4292169167","https://openalex.org/W6601052344"],"related_works":["https://openalex.org/W2753615087","https://openalex.org/W3180803030","https://openalex.org/W4243576563","https://openalex.org/W2565280077","https://openalex.org/W1575240748","https://openalex.org/W2168550483","https://openalex.org/W2316890442","https://openalex.org/W2782503170","https://openalex.org/W2047684617","https://openalex.org/W2143690511"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}