{"id":"https://openalex.org/W196381293","doi":"https://doi.org/10.1007/978-3-642-30341-8_16","title":"Hardware Implementations of Rough Set Methods in Programmable Logic Devices","display_name":"Hardware Implementations of Rough Set Methods in Programmable Logic Devices","publication_year":2012,"publication_date":"2012-08-13","ids":{"openalex":"https://openalex.org/W196381293","doi":"https://doi.org/10.1007/978-3-642-30341-8_16","mag":"196381293"},"language":"en","primary_location":{"id":"doi:10.1007/978-3-642-30341-8_16","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-642-30341-8_16","pdf_url":null,"source":{"id":"https://openalex.org/S4210212400","display_name":"Intelligent systems reference library","issn_l":"1868-4394","issn":["1868-4394","1868-4408"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319965","host_organization_name":"Springer Nature","host_organization_lineage":["https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Intelligent Systems Reference Library","raw_type":"book-chapter"},"type":"book-chapter","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5080392041","display_name":"Maciej Kopczy\u0144ski","orcid":"https://orcid.org/0000-0001-7846-1075"},"institutions":[{"id":"https://openalex.org/I1323121030","display_name":"Bialystok University of Technology","ror":"https://ror.org/02bzfsy61","country_code":"PL","type":"education","lineage":["https://openalex.org/I1323121030"]}],"countries":["PL"],"is_corresponding":false,"raw_author_name":"Maciej Kopczy\u0144ski","raw_affiliation_strings":["Department of Computer Science, Bia\u0142ystok University of Technology, Bia\u0142ystok, Poland","Bialystok University of Technology"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, Bia\u0142ystok University of Technology, Bia\u0142ystok, Poland","institution_ids":["https://openalex.org/I1323121030"]},{"raw_affiliation_string":"Bialystok University of Technology","institution_ids":["https://openalex.org/I1323121030"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5040029138","display_name":"Jaros\u0142aw Stepaniuk","orcid":"https://orcid.org/0000-0002-6517-850X"},"institutions":[{"id":"https://openalex.org/I1323121030","display_name":"Bialystok University of Technology","ror":"https://ror.org/02bzfsy61","country_code":"PL","type":"education","lineage":["https://openalex.org/I1323121030"]}],"countries":["PL"],"is_corresponding":false,"raw_author_name":"Jaros\u0142aw Stepaniuk","raw_affiliation_strings":["Department of Computer Science, Bia\u0142ystok University of Technology, Bia\u0142ystok, Poland","Bialystok University of Technology"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science, Bia\u0142ystok University of Technology, Bia\u0142ystok, Poland","institution_ids":["https://openalex.org/I1323121030"]},{"raw_affiliation_string":"Bialystok University of Technology","institution_ids":["https://openalex.org/I1323121030"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.5392,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.80157662,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"309","last_page":"321"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11063","display_name":"Rough Sets and Fuzzy Logic","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11063","display_name":"Rough Sets and Fuzzy Logic","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14351","display_name":"Statistical and Computational Modeling","score":0.9750000238418579,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14339","display_name":"Image Processing and 3D Reconstruction","score":0.9409000277519226,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8246837854385376},{"id":"https://openalex.org/keywords/realization","display_name":"Realization (probability)","score":0.7103793621063232},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.7035937905311584},{"id":"https://openalex.org/keywords/programmable-array-logic","display_name":"Programmable Array Logic","score":0.674708902835846},{"id":"https://openalex.org/keywords/simple-programmable-logic-device","display_name":"Simple programmable logic device","score":0.6479716300964355},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.636516809463501},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.6053332090377808},{"id":"https://openalex.org/keywords/erasable-programmable-logic-device","display_name":"Erasable programmable logic device","score":0.5388981699943542},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.5379721522331238},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.5319502949714661},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.47236257791519165},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.44982028007507324},{"id":"https://openalex.org/keywords/macrocell-array","display_name":"Macrocell array","score":0.4352349638938904},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.39108386635780334},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.332850843667984},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.26047080755233765},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.2472948133945465},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.13784372806549072},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.0965585708618164},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.09303086996078491}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8246837854385376},{"id":"https://openalex.org/C2781089630","wikidata":"https://www.wikidata.org/wiki/Q21856745","display_name":"Realization (probability)","level":2,"score":0.7103793621063232},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.7035937905311584},{"id":"https://openalex.org/C113323844","wikidata":"https://www.wikidata.org/wiki/Q1378651","display_name":"Programmable Array Logic","level":5,"score":0.674708902835846},{"id":"https://openalex.org/C34370810","wikidata":"https://www.wikidata.org/wiki/Q3961319","display_name":"Simple programmable logic device","level":5,"score":0.6479716300964355},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.636516809463501},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.6053332090377808},{"id":"https://openalex.org/C110050671","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Erasable programmable logic device","level":5,"score":0.5388981699943542},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.5379721522331238},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.5319502949714661},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.47236257791519165},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.44982028007507324},{"id":"https://openalex.org/C142278197","wikidata":"https://www.wikidata.org/wiki/Q4284934","display_name":"Macrocell array","level":5,"score":0.4352349638938904},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.39108386635780334},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.332850843667984},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.26047080755233765},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.2472948133945465},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.13784372806549072},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0965585708618164},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.09303086996078491},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/978-3-642-30341-8_16","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-642-30341-8_16","pdf_url":null,"source":{"id":"https://openalex.org/S4210212400","display_name":"Intelligent systems reference library","issn_l":"1868-4394","issn":["1868-4394","1868-4408"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319965","host_organization_name":"Springer Nature","host_organization_lineage":["https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Intelligent Systems Reference Library","raw_type":"book-chapter"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W88431461","https://openalex.org/W90286923","https://openalex.org/W149306696","https://openalex.org/W617158045","https://openalex.org/W1514599374","https://openalex.org/W1589060019","https://openalex.org/W1591618909","https://openalex.org/W1682011459","https://openalex.org/W1796734457","https://openalex.org/W2093299253","https://openalex.org/W2101635030","https://openalex.org/W2143451122","https://openalex.org/W2225754340","https://openalex.org/W2524978612","https://openalex.org/W6603667580"],"related_works":["https://openalex.org/W1528933814","https://openalex.org/W3013792460","https://openalex.org/W3117015220","https://openalex.org/W2014165129","https://openalex.org/W1904803855","https://openalex.org/W3022525969","https://openalex.org/W2376859467","https://openalex.org/W2466591189","https://openalex.org/W4389045693","https://openalex.org/W2054740893"],"abstract_inverted_index":null,"counts_by_year":[{"year":2021,"cited_by_count":3},{"year":2020,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
