{"id":"https://openalex.org/W1542332425","doi":"https://doi.org/10.1007/978-3-540-93799-9_3","title":"Performance Characterization of Itanium\u00ae 2-Based Montecito Processor","display_name":"Performance Characterization of Itanium\u00ae 2-Based Montecito Processor","publication_year":2009,"publication_date":"2009-01-01","ids":{"openalex":"https://openalex.org/W1542332425","doi":"https://doi.org/10.1007/978-3-540-93799-9_3","mag":"1542332425"},"language":"en","primary_location":{"id":"doi:10.1007/978-3-540-93799-9_3","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-540-93799-9_3","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},"type":"book-chapter","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5039737480","display_name":"Darshan Desai","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Darshan Desai","raw_affiliation_strings":["Intel Compiler Lab, Intel Corporation, Santa Clara, CA 95050, USA"],"affiliations":[{"raw_affiliation_string":"Intel Compiler Lab, Intel Corporation, Santa Clara, CA 95050, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036037219","display_name":"Gerolf F. Hoflehner","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Gerolf F. Hoflehner","raw_affiliation_strings":["Intel Compiler Lab, Intel Corporation, Santa Clara, CA 95050, USA"],"affiliations":[{"raw_affiliation_string":"Intel Compiler Lab, Intel Corporation, Santa Clara, CA 95050, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047988079","display_name":"Arun Kejariwal","orcid":"https://orcid.org/0009-0006-6172-2973"},"institutions":[{"id":"https://openalex.org/I204250578","display_name":"University of California, Irvine","ror":"https://ror.org/04gyf1771","country_code":"US","type":"education","lineage":["https://openalex.org/I204250578"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Arun Kejariwal","raw_affiliation_strings":["Center for Embedded Computer Systems, University of California, Irvine, Irvine, CA 92697, USA"],"affiliations":[{"raw_affiliation_string":"Center for Embedded Computer Systems, University of California, Irvine, Irvine, CA 92697, USA","institution_ids":["https://openalex.org/I204250578"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103555944","display_name":"Daniel M. Lavery","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Daniel M. Lavery","raw_affiliation_strings":["Intel Compiler Lab, Intel Corporation, Santa Clara, CA 95050, USA"],"affiliations":[{"raw_affiliation_string":"Intel Compiler Lab, Intel Corporation, Santa Clara, CA 95050, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102229114","display_name":"Alexandru Nicolau","orcid":null},"institutions":[{"id":"https://openalex.org/I204250578","display_name":"University of California, Irvine","ror":"https://ror.org/04gyf1771","country_code":"US","type":"education","lineage":["https://openalex.org/I204250578"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Alexandru Nicolau","raw_affiliation_strings":["Center for Embedded Computer Systems, University of California, Irvine, Irvine, CA 92697, USA"],"affiliations":[{"raw_affiliation_string":"Center for Embedded Computer Systems, University of California, Irvine, Irvine, CA 92697, USA","institution_ids":["https://openalex.org/I204250578"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110285605","display_name":"Alexander V. Veidenbaum","orcid":null},"institutions":[{"id":"https://openalex.org/I204250578","display_name":"University of California, Irvine","ror":"https://ror.org/04gyf1771","country_code":"US","type":"education","lineage":["https://openalex.org/I204250578"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Alexander V. Veidenbaum","raw_affiliation_strings":["Center for Embedded Computer Systems, University of California, Irvine, Irvine, CA 92697, USA"],"affiliations":[{"raw_affiliation_string":"Center for Embedded Computer Systems, University of California, Irvine, Irvine, CA 92697, USA","institution_ids":["https://openalex.org/I204250578"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5078428831","display_name":"C. McNairy","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Cameron McNairy","raw_affiliation_strings":["Intel Compiler Lab, Intel Corporation, Santa Clara, CA 95050, USA"],"affiliations":[{"raw_affiliation_string":"Intel Compiler Lab, Intel Corporation, Santa Clara, CA 95050, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5039737480"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":{"value":5000,"currency":"EUR","value_usd":5392},"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.12556054,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"36","last_page":"56"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8828730583190918},{"id":"https://openalex.org/keywords/spec#","display_name":"Spec#","score":0.7821100950241089},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.7296396493911743},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.6757206916809082},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5249036550521851},{"id":"https://openalex.org/keywords/translation-lookaside-buffer","display_name":"Translation lookaside buffer","score":0.5223708748817444},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.49921488761901855},{"id":"https://openalex.org/keywords/fortran","display_name":"Fortran","score":0.4728301465511322},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.42302876710891724},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.42291539907455444},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.24542784690856934},{"id":"https://openalex.org/keywords/physical-address","display_name":"Physical address","score":0.09431576728820801}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8828730583190918},{"id":"https://openalex.org/C2778565505","wikidata":"https://www.wikidata.org/wiki/Q2207566","display_name":"Spec#","level":2,"score":0.7821100950241089},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.7296396493911743},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.6757206916809082},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5249036550521851},{"id":"https://openalex.org/C116007543","wikidata":"https://www.wikidata.org/wiki/Q1071403","display_name":"Translation lookaside buffer","level":4,"score":0.5223708748817444},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.49921488761901855},{"id":"https://openalex.org/C2778241615","wikidata":"https://www.wikidata.org/wiki/Q83303","display_name":"Fortran","level":2,"score":0.4728301465511322},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.42302876710891724},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.42291539907455444},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.24542784690856934},{"id":"https://openalex.org/C41036726","wikidata":"https://www.wikidata.org/wiki/Q844824","display_name":"Physical address","level":3,"score":0.09431576728820801},{"id":"https://openalex.org/C136085584","wikidata":"https://www.wikidata.org/wiki/Q910289","display_name":"Overlay","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/978-3-540-93799-9_3","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-540-93799-9_3","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5699999928474426,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W2052839611","https://openalex.org/W2070946250","https://openalex.org/W2126833541","https://openalex.org/W2130363691","https://openalex.org/W2141425839"],"related_works":["https://openalex.org/W1519027223","https://openalex.org/W98496534","https://openalex.org/W2070946250","https://openalex.org/W2109692305","https://openalex.org/W189970040","https://openalex.org/W1491189730","https://openalex.org/W1489284269","https://openalex.org/W2737587281","https://openalex.org/W2121380786","https://openalex.org/W2392239432"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
