{"id":"https://openalex.org/W1500469887","doi":"https://doi.org/10.1007/978-3-540-92990-1_20","title":"A Framework for Task Scheduling and Memory Partitioning for Multi-Processor System-on-Chip","display_name":"A Framework for Task Scheduling and Memory Partitioning for Multi-Processor System-on-Chip","publication_year":2008,"publication_date":"2008-12-23","ids":{"openalex":"https://openalex.org/W1500469887","doi":"https://doi.org/10.1007/978-3-540-92990-1_20","mag":"1500469887"},"language":"en","primary_location":{"id":"doi:10.1007/978-3-540-92990-1_20","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-540-92990-1_20","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},"type":"book-chapter","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5005484411","display_name":"Hassan Salamy","orcid":"https://orcid.org/0000-0003-1314-1702"},"institutions":[{"id":"https://openalex.org/I121820613","display_name":"Louisiana State University","ror":"https://ror.org/05ect4e57","country_code":"US","type":"education","lineage":["https://openalex.org/I121820613"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Hassan Salamy","raw_affiliation_strings":["Department of Electrical and Computer Engineering and Center for Computation and Technology, Louisiana State University, Baton Rouge, LA 70803, USA","Department of Electrical and Computer Engineering and Center for Computation and Technology, Louisiana State University, Baton Rouge, USA LA 70803#TAB#"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering and Center for Computation and Technology, Louisiana State University, Baton Rouge, LA 70803, USA","institution_ids":["https://openalex.org/I121820613"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering and Center for Computation and Technology, Louisiana State University, Baton Rouge, USA LA 70803#TAB#","institution_ids":["https://openalex.org/I121820613"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5057117526","display_name":"J. Ramanujam","orcid":"https://orcid.org/0000-0002-4349-1327"},"institutions":[{"id":"https://openalex.org/I121820613","display_name":"Louisiana State University","ror":"https://ror.org/05ect4e57","country_code":"US","type":"education","lineage":["https://openalex.org/I121820613"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J. Ramanujam","raw_affiliation_strings":["Department of Electrical and Computer Engineering and Center for Computation and Technology, Louisiana State University, Baton Rouge, LA 70803, USA","Department of Electrical and Computer Engineering and Center for Computation and Technology, Louisiana State University, Baton Rouge, USA LA 70803#TAB#"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering and Center for Computation and Technology, Louisiana State University, Baton Rouge, LA 70803, USA","institution_ids":["https://openalex.org/I121820613"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering and Center for Computation and Technology, Louisiana State University, Baton Rouge, USA LA 70803#TAB#","institution_ids":["https://openalex.org/I121820613"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5005484411"],"corresponding_institution_ids":["https://openalex.org/I121820613"],"apc_list":{"value":5000,"currency":"EUR","value_usd":5392},"apc_paid":null,"fwci":1.3203,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.77881356,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"263","last_page":"277"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8868634700775146},{"id":"https://openalex.org/keywords/mpsoc","display_name":"MPSoC","score":0.8299331665039062},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.6292338967323303},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.5870500802993774},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5543861389160156},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5515322089195251},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.49187684059143066},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.48581504821777344},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3914477527141571},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.35733842849731445},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.12897968292236328}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8868634700775146},{"id":"https://openalex.org/C2777187653","wikidata":"https://www.wikidata.org/wiki/Q975106","display_name":"MPSoC","level":3,"score":0.8299331665039062},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.6292338967323303},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.5870500802993774},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5543861389160156},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5515322089195251},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.49187684059143066},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.48581504821777344},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3914477527141571},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.35733842849731445},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.12897968292236328},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1007/978-3-540-92990-1_20","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-540-92990-1_20","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},{"id":"pmh:oai:HAL:inria-00446288v1","is_oa":false,"landing_page_url":"https://inria.hal.science/inria-00446288","pdf_url":null,"source":{"id":"https://openalex.org/S4406922276","display_name":"INRIA a CCSD electronic archive server","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"HiPEAC 2009 - High Performance and Embedded Architectures and Compilers, Jan 2009, Paphos, Cyprus. &#x27E8;10.1007/978-3-540-92990-1_20&#x27E9;","raw_type":"Conference papers"},{"id":"pmh:oai:repository.lsu.edu:eecs_pubs-2616","is_oa":false,"landing_page_url":"https://repository.lsu.edu/eecs_pubs/1614","pdf_url":null,"source":{"id":"https://openalex.org/S4210169993","display_name":"Civil War Book Review","issn_l":"1528-6592","issn":["1528-6592"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/P4310315936","host_organization_name":"Louisiana State University","host_organization_lineage":["https://openalex.org/P4310315936"],"host_organization_lineage_names":["Louisiana State University"],"type":"journal"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Faculty Publications","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":26,"referenced_works":["https://openalex.org/W149226439","https://openalex.org/W628293611","https://openalex.org/W1503117285","https://openalex.org/W1514004212","https://openalex.org/W1559272609","https://openalex.org/W1580327099","https://openalex.org/W1816728452","https://openalex.org/W1969288309","https://openalex.org/W1973531467","https://openalex.org/W2053444453","https://openalex.org/W2054732504","https://openalex.org/W2086807722","https://openalex.org/W2104225326","https://openalex.org/W2105778948","https://openalex.org/W2113870209","https://openalex.org/W2131548569","https://openalex.org/W2136453233","https://openalex.org/W2147116847","https://openalex.org/W2149590159","https://openalex.org/W2158327022","https://openalex.org/W2161147079","https://openalex.org/W2163270257","https://openalex.org/W2506983566","https://openalex.org/W2907064665","https://openalex.org/W4241465371","https://openalex.org/W4246052078"],"related_works":["https://openalex.org/W4281711577","https://openalex.org/W2106200299","https://openalex.org/W2178653557","https://openalex.org/W2540211551","https://openalex.org/W2994908368","https://openalex.org/W1976012348","https://openalex.org/W2614713859","https://openalex.org/W2002682434","https://openalex.org/W4387782849","https://openalex.org/W2137671689"],"abstract_inverted_index":null,"counts_by_year":[{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":3},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
