{"id":"https://openalex.org/W1528167431","doi":"https://doi.org/10.1007/978-3-540-74442-9_50","title":"A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations","display_name":"A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations","publication_year":2007,"publication_date":"2007-08-20","ids":{"openalex":"https://openalex.org/W1528167431","doi":"https://doi.org/10.1007/978-3-540-74442-9_50","mag":"1528167431"},"language":"en","primary_location":{"id":"doi:10.1007/978-3-540-74442-9_50","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-540-74442-9_50","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5030782483","display_name":"Francesco Centurelli","orcid":"https://orcid.org/0000-0003-3880-2546"},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Francesco Centurelli","raw_affiliation_strings":["Dipartimento di Ingegneria Elettronica, Universit\u00e0 di Roma \"La Sapienza\", Via Eudossiana 18, 00184 Roma, Italy","Dipartimento di Ingegneria Elettronica, Universit\u00e0 di Roma \u2018La Sapienza\u2019, Roma, Italy#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Ingegneria Elettronica, Universit\u00e0 di Roma \"La Sapienza\", Via Eudossiana 18, 00184 Roma, Italy","institution_ids":["https://openalex.org/I861853513"]},{"raw_affiliation_string":"Dipartimento di Ingegneria Elettronica, Universit\u00e0 di Roma \u2018La Sapienza\u2019, Roma, Italy#TAB#","institution_ids":["https://openalex.org/I861853513"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078031617","display_name":"Luca Giancane","orcid":"https://orcid.org/0000-0002-7473-1055"},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Luca Giancane","raw_affiliation_strings":["Dipartimento di Ingegneria Elettronica, Universit\u00e0 di Roma \"La Sapienza\", Via Eudossiana 18, 00184 Roma, Italy","Dipartimento di Ingegneria Elettronica, Universit\u00e0 di Roma \u2018La Sapienza\u2019, Roma, Italy#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Ingegneria Elettronica, Universit\u00e0 di Roma \"La Sapienza\", Via Eudossiana 18, 00184 Roma, Italy","institution_ids":["https://openalex.org/I861853513"]},{"raw_affiliation_string":"Dipartimento di Ingegneria Elettronica, Universit\u00e0 di Roma \u2018La Sapienza\u2019, Roma, Italy#TAB#","institution_ids":["https://openalex.org/I861853513"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5067054447","display_name":"Mauro Olivieri","orcid":"https://orcid.org/0000-0002-0214-9904"},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Mauro Olivieri","raw_affiliation_strings":["Dipartimento di Ingegneria Elettronica, Universit\u00e0 di Roma \"La Sapienza\", Via Eudossiana 18, 00184 Roma, Italy","Dipartimento di Ingegneria Elettronica, Universit\u00e0 di Roma \u2018La Sapienza\u2019, Roma, Italy#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Ingegneria Elettronica, Universit\u00e0 di Roma \"La Sapienza\", Via Eudossiana 18, 00184 Roma, Italy","institution_ids":["https://openalex.org/I861853513"]},{"raw_affiliation_string":"Dipartimento di Ingegneria Elettronica, Universit\u00e0 di Roma \u2018La Sapienza\u2019, Roma, Italy#TAB#","institution_ids":["https://openalex.org/I861853513"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010336494","display_name":"Giuseppe Scotti","orcid":"https://orcid.org/0000-0002-5650-8212"},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Giuseppe Scotti","raw_affiliation_strings":["Dipartimento di Ingegneria Elettronica, Universit\u00e0 di Roma \"La Sapienza\", Via Eudossiana 18, 00184 Roma, Italy","Dipartimento di Ingegneria Elettronica, Universit\u00e0 di Roma \u2018La Sapienza\u2019, Roma, Italy#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Ingegneria Elettronica, Universit\u00e0 di Roma \"La Sapienza\", Via Eudossiana 18, 00184 Roma, Italy","institution_ids":["https://openalex.org/I861853513"]},{"raw_affiliation_string":"Dipartimento di Ingegneria Elettronica, Universit\u00e0 di Roma \u2018La Sapienza\u2019, Roma, Italy#TAB#","institution_ids":["https://openalex.org/I861853513"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5068452963","display_name":"Alessandro Trifiletti","orcid":"https://orcid.org/0000-0001-6231-4273"},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Alessandro Trifiletti","raw_affiliation_strings":["Dipartimento di Ingegneria Elettronica, Universit\u00e0 di Roma \"La Sapienza\", Via Eudossiana 18, 00184 Roma, Italy","Dipartimento di Ingegneria Elettronica, Universit\u00e0 di Roma \u2018La Sapienza\u2019, Roma, Italy#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dipartimento di Ingegneria Elettronica, Universit\u00e0 di Roma \"La Sapienza\", Via Eudossiana 18, 00184 Roma, Italy","institution_ids":["https://openalex.org/I861853513"]},{"raw_affiliation_string":"Dipartimento di Ingegneria Elettronica, Universit\u00e0 di Roma \u2018La Sapienza\u2019, Roma, Italy#TAB#","institution_ids":["https://openalex.org/I861853513"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I861853513"],"apc_list":{"value":5000,"currency":"EUR","value_usd":5392},"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"516","last_page":"525"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7776206731796265},{"id":"https://openalex.org/keywords/monte-carlo-method","display_name":"Monte Carlo method","score":0.6765100955963135},{"id":"https://openalex.org/keywords/logic-simulation","display_name":"Logic simulation","score":0.6632916331291199},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.5570091605186462},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5048125982284546},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.480532705783844},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.47007423639297485},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.45589426159858704},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.4382190704345703},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.42899808287620544},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3964361846446991},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3663318157196045},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.1816059648990631},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.17779597640037537},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.1598253846168518},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.14968246221542358},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.11165747046470642},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1041337251663208}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7776206731796265},{"id":"https://openalex.org/C19499675","wikidata":"https://www.wikidata.org/wiki/Q232207","display_name":"Monte Carlo method","level":2,"score":0.6765100955963135},{"id":"https://openalex.org/C64859876","wikidata":"https://www.wikidata.org/wiki/Q173673","display_name":"Logic simulation","level":3,"score":0.6632916331291199},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.5570091605186462},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5048125982284546},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.480532705783844},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.47007423639297485},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.45589426159858704},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.4382190704345703},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.42899808287620544},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3964361846446991},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3663318157196045},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.1816059648990631},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.17779597640037537},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.1598253846168518},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.14968246221542358},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.11165747046470642},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1041337251663208},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1007/978-3-540-74442-9_50","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-540-74442-9_50","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},{"id":"pmh:oai:iris.uniroma1.it:11573/367810","is_oa":false,"landing_page_url":"http://hdl.handle.net/11573/367810","pdf_url":null,"source":{"id":"https://openalex.org/S4377196107","display_name":"IRIS Research product catalog (Sapienza University of Rome)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W574322001","https://openalex.org/W1517072937","https://openalex.org/W1525409241","https://openalex.org/W1527137186","https://openalex.org/W1773690954","https://openalex.org/W1999781385","https://openalex.org/W2033443176","https://openalex.org/W2035894108","https://openalex.org/W2062395401","https://openalex.org/W2105597240","https://openalex.org/W2107996516","https://openalex.org/W2113407574","https://openalex.org/W2115435370","https://openalex.org/W2119821681","https://openalex.org/W2126827022","https://openalex.org/W2136328167","https://openalex.org/W2150731325","https://openalex.org/W2156016717","https://openalex.org/W2162935501","https://openalex.org/W2165523058","https://openalex.org/W2167620266","https://openalex.org/W3198221827","https://openalex.org/W4239545803","https://openalex.org/W4240067961"],"related_works":["https://openalex.org/W2136295006","https://openalex.org/W2165480138","https://openalex.org/W2107240870","https://openalex.org/W2107517480","https://openalex.org/W4231001357","https://openalex.org/W2131024837","https://openalex.org/W2539742022","https://openalex.org/W2063218591","https://openalex.org/W4210326786","https://openalex.org/W2143529626"],"abstract_inverted_index":null,"counts_by_year":[{"year":2025,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
