{"id":"https://openalex.org/W1546793464","doi":"https://doi.org/10.1007/978-3-540-71431-6_9","title":"Designing Heterogeneous FPGAs with Multiple SBs","display_name":"Designing Heterogeneous FPGAs with Multiple SBs","publication_year":2007,"publication_date":"2007-06-03","ids":{"openalex":"https://openalex.org/W1546793464","doi":"https://doi.org/10.1007/978-3-540-71431-6_9","mag":"1546793464"},"language":"en","primary_location":{"id":"doi:10.1007/978-3-540-71431-6_9","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-540-71431-6_9","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5072486756","display_name":"Kostas Siozios","orcid":"https://orcid.org/0000-0002-0285-2202"},"institutions":[{"id":"https://openalex.org/I147962203","display_name":"Democritus University of Thrace","ror":"https://ror.org/03bfqnx40","country_code":"GR","type":"education","lineage":["https://openalex.org/I147962203"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Kostas Siozios","raw_affiliation_strings":["VLSI Design and Testing Center, Department of Electrical and Computer Engineering, Democritus University of Thrace, 67100, Xanthi, Greece","VLSI Design and Testing Center, Dept. of Electrical & Computer Eng., Democritus Univ. of Thrace, Xanthi, Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"VLSI Design and Testing Center, Department of Electrical and Computer Engineering, Democritus University of Thrace, 67100, Xanthi, Greece","institution_ids":["https://openalex.org/I147962203"]},{"raw_affiliation_string":"VLSI Design and Testing Center, Dept. of Electrical & Computer Eng., Democritus Univ. of Thrace, Xanthi, Greece","institution_ids":["https://openalex.org/I147962203"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063163548","display_name":"Stelios Mamagkakis","orcid":null},"institutions":[{"id":"https://openalex.org/I147962203","display_name":"Democritus University of Thrace","ror":"https://ror.org/03bfqnx40","country_code":"GR","type":"education","lineage":["https://openalex.org/I147962203"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Stelios Mamagkakis","raw_affiliation_strings":["VLSI Design and Testing Center, Department of Electrical and Computer Engineering, Democritus University of Thrace, 67100, Xanthi, Greece","VLSI Design and Testing Center, Dept. of Electrical & Computer Eng., Democritus Univ. of Thrace, Xanthi, Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"VLSI Design and Testing Center, Department of Electrical and Computer Engineering, Democritus University of Thrace, 67100, Xanthi, Greece","institution_ids":["https://openalex.org/I147962203"]},{"raw_affiliation_string":"VLSI Design and Testing Center, Dept. of Electrical & Computer Eng., Democritus Univ. of Thrace, Xanthi, Greece","institution_ids":["https://openalex.org/I147962203"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043131021","display_name":"Dimitrios Soudris","orcid":"https://orcid.org/0000-0002-6930-6847"},"institutions":[{"id":"https://openalex.org/I147962203","display_name":"Democritus University of Thrace","ror":"https://ror.org/03bfqnx40","country_code":"GR","type":"education","lineage":["https://openalex.org/I147962203"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Dimitrios Soudris","raw_affiliation_strings":["VLSI Design and Testing Center, Department of Electrical and Computer Engineering, Democritus University of Thrace, 67100, Xanthi, Greece","VLSI Design and Testing Center, Dept. of Electrical & Computer Eng., Democritus Univ. of Thrace, Xanthi, Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"VLSI Design and Testing Center, Department of Electrical and Computer Engineering, Democritus University of Thrace, 67100, Xanthi, Greece","institution_ids":["https://openalex.org/I147962203"]},{"raw_affiliation_string":"VLSI Design and Testing Center, Dept. of Electrical & Computer Eng., Democritus Univ. of Thrace, Xanthi, Greece","institution_ids":["https://openalex.org/I147962203"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5105413530","display_name":"Antonios Thanailakis","orcid":null},"institutions":[{"id":"https://openalex.org/I147962203","display_name":"Democritus University of Thrace","ror":"https://ror.org/03bfqnx40","country_code":"GR","type":"education","lineage":["https://openalex.org/I147962203"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Antonios Thanailakis","raw_affiliation_strings":["VLSI Design and Testing Center, Department of Electrical and Computer Engineering, Democritus University of Thrace, 67100, Xanthi, Greece","VLSI Design and Testing Center, Dept. of Electrical & Computer Eng., Democritus Univ. of Thrace, Xanthi, Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"VLSI Design and Testing Center, Department of Electrical and Computer Engineering, Democritus University of Thrace, 67100, Xanthi, Greece","institution_ids":["https://openalex.org/I147962203"]},{"raw_affiliation_string":"VLSI Design and Testing Center, Dept. of Electrical & Computer Eng., Democritus Univ. of Thrace, Xanthi, Greece","institution_ids":["https://openalex.org/I147962203"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I147962203"],"apc_list":{"value":5000,"currency":"EUR","value_usd":5392},"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.02432066,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"91","last_page":"96"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7546384334564209},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.7193385362625122},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6500172019004822},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.6452493667602539},{"id":"https://openalex.org/keywords/energy-consumption","display_name":"Energy consumption","score":0.610640287399292},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5844335556030273},{"id":"https://openalex.org/keywords/energy","display_name":"Energy (signal processing)","score":0.5641343593597412},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.4577125906944275},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.450111985206604},{"id":"https://openalex.org/keywords/product","display_name":"Product (mathematics)","score":0.4461006820201874},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.42350366711616516},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.33843064308166504},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23761031031608582},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.15620329976081848},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.14537960290908813},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.12921404838562012}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7546384334564209},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.7193385362625122},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6500172019004822},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.6452493667602539},{"id":"https://openalex.org/C2780165032","wikidata":"https://www.wikidata.org/wiki/Q16869822","display_name":"Energy consumption","level":2,"score":0.610640287399292},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5844335556030273},{"id":"https://openalex.org/C186370098","wikidata":"https://www.wikidata.org/wiki/Q442787","display_name":"Energy (signal processing)","level":2,"score":0.5641343593597412},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.4577125906944275},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.450111985206604},{"id":"https://openalex.org/C90673727","wikidata":"https://www.wikidata.org/wiki/Q901718","display_name":"Product (mathematics)","level":2,"score":0.4461006820201874},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.42350366711616516},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.33843064308166504},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23761031031608582},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.15620329976081848},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.14537960290908813},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.12921404838562012},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1007/978-3-540-71431-6_9","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-540-71431-6_9","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.131.3803","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.131.3803","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://vlsi.ee.duth.gr/amdrel/papers/arc2006siozios.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1522950391","https://openalex.org/W1523051745","https://openalex.org/W1604323946","https://openalex.org/W2116008950","https://openalex.org/W2168225933","https://openalex.org/W6600903635"],"related_works":["https://openalex.org/W2111241003","https://openalex.org/W2155019192","https://openalex.org/W2014709025","https://openalex.org/W2110265185","https://openalex.org/W3146360095","https://openalex.org/W2184011203","https://openalex.org/W1967938402","https://openalex.org/W2386041993","https://openalex.org/W1608572506","https://openalex.org/W2154356865"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2026-08-04T08:18:43.703281","created_date":"2025-10-10T00:00:00"}
