{"id":"https://openalex.org/W1594330419","doi":"https://doi.org/10.1007/978-3-540-48765-4_26","title":"New Directions in Debugging Hardware Designs","display_name":"New Directions in Debugging Hardware Designs","publication_year":1999,"publication_date":"1999-01-01","ids":{"openalex":"https://openalex.org/W1594330419","doi":"https://doi.org/10.1007/978-3-540-48765-4_26","mag":"1594330419"},"language":"en","primary_location":{"id":"doi:10.1007/978-3-540-48765-4_26","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-540-48765-4_26","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},"type":"book-chapter","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5011388533","display_name":"Franz Wotawa","orcid":"https://orcid.org/0000-0002-0462-2283"},"institutions":[{"id":"https://openalex.org/I145847075","display_name":"TU Wien","ror":"https://ror.org/04d836q62","country_code":"AT","type":"education","lineage":["https://openalex.org/I145847075"]}],"countries":["AT"],"is_corresponding":true,"raw_author_name":"Franz Wotawa","raw_affiliation_strings":["Institut f\u00fcr Informationssysteme, Technische Universit\u00e4t Wien, Paniglgasse 16, A-1040, Wien, Austria"],"affiliations":[{"raw_affiliation_string":"Institut f\u00fcr Informationssysteme, Technische Universit\u00e4t Wien, Paniglgasse 16, A-1040, Wien, Austria","institution_ids":["https://openalex.org/I145847075"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5011388533"],"corresponding_institution_ids":["https://openalex.org/I145847075"],"apc_list":{"value":5000,"currency":"EUR","value_usd":5392},"apc_paid":null,"fwci":1.4774,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.79591837,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"226","last_page":"235"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10743","display_name":"Software Testing and Debugging Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10743","display_name":"Software Testing and Debugging Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12423","display_name":"Software Reliability and Analysis Research","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.9965000152587891,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8731075525283813},{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.8698467016220093},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.8694188594818115},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.5549213290214539},{"id":"https://openalex.org/keywords/component","display_name":"Component (thermodynamics)","score":0.5497756600379944},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.48993033170700073},{"id":"https://openalex.org/keywords/automation","display_name":"Automation","score":0.4822421967983246},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.44525980949401855},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.443536639213562},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.42932260036468506},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.41539114713668823},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4067494571208954},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.39477115869522095},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.36118608713150024},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.30369290709495544},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.16768255829811096},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.142807275056839},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.12735870480537415}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8731075525283813},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.8698467016220093},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.8694188594818115},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.5549213290214539},{"id":"https://openalex.org/C168167062","wikidata":"https://www.wikidata.org/wiki/Q1117970","display_name":"Component (thermodynamics)","level":2,"score":0.5497756600379944},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.48993033170700073},{"id":"https://openalex.org/C115901376","wikidata":"https://www.wikidata.org/wiki/Q184199","display_name":"Automation","level":2,"score":0.4822421967983246},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.44525980949401855},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.443536639213562},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.42932260036468506},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.41539114713668823},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4067494571208954},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.39477115869522095},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.36118608713150024},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.30369290709495544},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.16768255829811096},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.142807275056839},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.12735870480537415},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1007/978-3-540-48765-4_26","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-540-48765-4_26","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.18.1314","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.18.1314","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.dbai.tuwien.ac.at/staff/wotawa/ieaaie99b.ps.gz","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.94.8198","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.94.8198","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ist.tugraz.at/DEV/download/conferences/debugging.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.47999998927116394,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W194442520","https://openalex.org/W289669055","https://openalex.org/W1525885020","https://openalex.org/W1571486933","https://openalex.org/W1594330419","https://openalex.org/W1797873548","https://openalex.org/W2097293815","https://openalex.org/W2108309071","https://openalex.org/W2116938596","https://openalex.org/W2140627345","https://openalex.org/W2144386448","https://openalex.org/W2293624369","https://openalex.org/W3143401387","https://openalex.org/W3153341211"],"related_works":["https://openalex.org/W2384838054","https://openalex.org/W2069295582","https://openalex.org/W2363829830","https://openalex.org/W1843355381","https://openalex.org/W1530924151","https://openalex.org/W2370873755","https://openalex.org/W2534549730","https://openalex.org/W1873290954","https://openalex.org/W1492116303","https://openalex.org/W2077870657"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
