{"id":"https://openalex.org/W1483293529","doi":"https://doi.org/10.1007/978-3-540-48302-1_33","title":"Synthia: Synthesis of Interacting Automata Targeting LUT-based FPGAs","display_name":"Synthia: Synthesis of Interacting Automata Targeting LUT-based FPGAs","publication_year":1999,"publication_date":"1999-01-01","ids":{"openalex":"https://openalex.org/W1483293529","doi":"https://doi.org/10.1007/978-3-540-48302-1_33","mag":"1483293529"},"language":"en","primary_location":{"id":"doi:10.1007/978-3-540-48302-1_33","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-540-48302-1_33","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},"type":"book-chapter","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5029829952","display_name":"George A. Constantinides","orcid":"https://orcid.org/0000-0002-0201-310X"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"George A. Constantinides","raw_affiliation_strings":["Electrical and Electronic Engineering Dept., Imperial College, London, U.K"],"affiliations":[{"raw_affiliation_string":"Electrical and Electronic Engineering Dept., Imperial College, London, U.K","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091532722","display_name":"Peter Y. K. Cheung","orcid":"https://orcid.org/0000-0002-8236-1816"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Peter Y. K. Cheung","raw_affiliation_strings":["Electrical and Electronic Engineering Dept., Imperial College, London, U.K"],"affiliations":[{"raw_affiliation_string":"Electrical and Electronic Engineering Dept., Imperial College, London, U.K","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5057940557","display_name":"Wayne Luk","orcid":"https://orcid.org/0000-0002-6750-927X"},"institutions":[{"id":"https://openalex.org/I47508984","display_name":"Imperial College London","ror":"https://ror.org/041kmwe10","country_code":"GB","type":"education","lineage":["https://openalex.org/I47508984"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"Wayne Luk","raw_affiliation_strings":["Department of Computing, Imperial College, London, U.K"],"affiliations":[{"raw_affiliation_string":"Department of Computing, Imperial College, London, U.K","institution_ids":["https://openalex.org/I47508984"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5029829952"],"corresponding_institution_ids":[],"apc_list":{"value":5000,"currency":"EUR","value_usd":5392},"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.15052854,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"323","last_page":"332"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11975","display_name":"Evolutionary Algorithms and Applications","score":0.9958000183105469,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8212911486625671},{"id":"https://openalex.org/keywords/finite-state-machine","display_name":"Finite-state machine","score":0.7477602362632751},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6769503355026245},{"id":"https://openalex.org/keywords/automaton","display_name":"Automaton","score":0.6587273478507996},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.5844618082046509},{"id":"https://openalex.org/keywords/decomposition","display_name":"Decomposition","score":0.5600148439407349},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.557496190071106},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.544792652130127},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.505280077457428},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.476968377828598},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.46551916003227234},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.43046483397483826},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.4199025332927704},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.37809306383132935},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3486631512641907},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2972983717918396},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.293818861246109},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.14626732468605042}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8212911486625671},{"id":"https://openalex.org/C167822520","wikidata":"https://www.wikidata.org/wiki/Q176452","display_name":"Finite-state machine","level":2,"score":0.7477602362632751},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6769503355026245},{"id":"https://openalex.org/C112505250","wikidata":"https://www.wikidata.org/wiki/Q787116","display_name":"Automaton","level":2,"score":0.6587273478507996},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.5844618082046509},{"id":"https://openalex.org/C124681953","wikidata":"https://www.wikidata.org/wiki/Q339062","display_name":"Decomposition","level":2,"score":0.5600148439407349},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.557496190071106},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.544792652130127},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.505280077457428},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.476968377828598},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.46551916003227234},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.43046483397483826},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.4199025332927704},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.37809306383132935},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3486631512641907},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2972983717918396},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.293818861246109},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.14626732468605042},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C18903297","wikidata":"https://www.wikidata.org/wiki/Q7150","display_name":"Ecology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1007/978-3-540-48302-1_33","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-540-48302-1_33","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.385.9130","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.385.9130","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://cas.ee.ic.ac.uk/people/gac1/pubs/GeorgeFPL99.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.65.975","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.65.975","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ee.ic.ac.uk/pcheung/publications/fpl99_synthia.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W142838967","https://openalex.org/W1500238730","https://openalex.org/W1511688816","https://openalex.org/W1522075243","https://openalex.org/W1544932170","https://openalex.org/W2059677035","https://openalex.org/W2105149330","https://openalex.org/W2136778154"],"related_works":["https://openalex.org/W2125609625","https://openalex.org/W2994343469","https://openalex.org/W2102777336","https://openalex.org/W3105918491","https://openalex.org/W1905312773","https://openalex.org/W1565986912","https://openalex.org/W2189515211","https://openalex.org/W2490069675","https://openalex.org/W2139569078","https://openalex.org/W4379115868"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
