{"id":"https://openalex.org/W2163530692","doi":"https://doi.org/10.1007/978-3-540-45234-8_31","title":"Performance and Area Modeling of Complete FPGA Designs in the Presence of Loop Transformations","display_name":"Performance and Area Modeling of Complete FPGA Designs in the Presence of Loop Transformations","publication_year":2003,"publication_date":"2003-01-01","ids":{"openalex":"https://openalex.org/W2163530692","doi":"https://doi.org/10.1007/978-3-540-45234-8_31","mag":"2163530692"},"language":"en","primary_location":{"id":"doi:10.1007/978-3-540-45234-8_31","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-540-45234-8_31","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},"type":"book-chapter","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5045645213","display_name":"K. R. Shesha Shayee","orcid":null},"institutions":[{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"K. R. Shesha Shayee","raw_affiliation_strings":["Information Sciences Institute, University of Southern California, 4676 Admiralty Way, Suite 1001, 90292, Marina del Rey, California, USA"],"affiliations":[{"raw_affiliation_string":"Information Sciences Institute, University of Southern California, 4676 Admiralty Way, Suite 1001, 90292, Marina del Rey, California, USA","institution_ids":["https://openalex.org/I1174212"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103206432","display_name":"Joon-Seok Park","orcid":"https://orcid.org/0009-0001-9427-6571"},"institutions":[{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Joonseok Park","raw_affiliation_strings":["Information Sciences Institute, University of Southern California, 4676 Admiralty Way, Suite 1001, 90292, Marina del Rey, California, USA"],"affiliations":[{"raw_affiliation_string":"Information Sciences Institute, University of Southern California, 4676 Admiralty Way, Suite 1001, 90292, Marina del Rey, California, USA","institution_ids":["https://openalex.org/I1174212"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5103547377","display_name":"Pedro C. Diniz","orcid":null},"institutions":[{"id":"https://openalex.org/I1174212","display_name":"University of Southern California","ror":"https://ror.org/03taz7m60","country_code":"US","type":"education","lineage":["https://openalex.org/I1174212"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Pedro C. Diniz","raw_affiliation_strings":["Information Sciences Institute, University of Southern California, 4676 Admiralty Way, Suite 1001, 90292, Marina del Rey, California, USA"],"affiliations":[{"raw_affiliation_string":"Information Sciences Institute, University of Southern California, 4676 Admiralty Way, Suite 1001, 90292, Marina del Rey, California, USA","institution_ids":["https://openalex.org/I1174212"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5045645213"],"corresponding_institution_ids":["https://openalex.org/I1174212"],"apc_list":{"value":5000,"currency":"EUR","value_usd":5392},"apc_paid":null,"fwci":1.9799,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":{"value":0.85076142,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"313","last_page":"323"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8768984079360962},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7610754370689392},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.677661120891571},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.6632043123245239},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.5824072957038879},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.5787222981452942},{"id":"https://openalex.org/keywords/limiting","display_name":"Limiting","score":0.5151764154434204},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4586487114429474},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.4584777355194092},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.444598913192749},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.44065943360328674},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3736079931259155},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.32121336460113525},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.19530752301216125}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8768984079360962},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7610754370689392},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.677661120891571},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.6632043123245239},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.5824072957038879},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.5787222981452942},{"id":"https://openalex.org/C188198153","wikidata":"https://www.wikidata.org/wiki/Q1613840","display_name":"Limiting","level":2,"score":0.5151764154434204},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4586487114429474},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.4584777355194092},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.444598913192749},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.44065943360328674},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3736079931259155},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.32121336460113525},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.19530752301216125},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/978-3-540-45234-8_31","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-540-45234-8_31","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1497684279","https://openalex.org/W1554668868","https://openalex.org/W1579143178","https://openalex.org/W1989435461","https://openalex.org/W2010074783","https://openalex.org/W2030934436","https://openalex.org/W2085054536","https://openalex.org/W2104121286","https://openalex.org/W2106472852","https://openalex.org/W2120961842","https://openalex.org/W2138010201","https://openalex.org/W2141955538","https://openalex.org/W2151820033","https://openalex.org/W2152506070","https://openalex.org/W2157828735","https://openalex.org/W4235903967"],"related_works":["https://openalex.org/W2125855853","https://openalex.org/W4245652312","https://openalex.org/W4313341326","https://openalex.org/W4282568311","https://openalex.org/W4313484792","https://openalex.org/W2951473296","https://openalex.org/W2883928845","https://openalex.org/W4288420200","https://openalex.org/W4285346947","https://openalex.org/W4365793791"],"abstract_inverted_index":null,"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":2},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}