{"id":"https://openalex.org/W1507713810","doi":"https://doi.org/10.1007/978-3-540-39920-9_2","title":"Limited Address Range Architecture for Reducing Code Size in Embedded Processors","display_name":"Limited Address Range Architecture for Reducing Code Size in Embedded Processors","publication_year":2003,"publication_date":"2003-01-01","ids":{"openalex":"https://openalex.org/W1507713810","doi":"https://doi.org/10.1007/978-3-540-39920-9_2","mag":"1507713810"},"language":"en","primary_location":{"id":"doi:10.1007/978-3-540-39920-9_2","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-540-39920-9_2","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100805804","display_name":"Quin Zhao","orcid":null},"institutions":[{"id":"https://openalex.org/I83019370","display_name":"Eindhoven University of Technology","ror":"https://ror.org/02c2kyt77","country_code":"NL","type":"education","lineage":["https://openalex.org/I83019370"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"Quin Zhao","raw_affiliation_strings":["Department of Electrical Engineering, Eindhoven University of Technology, P.O. Box 513, NL-5600, MB, Eindhoven, The Netherlands","EINDHOVEN UNIVERSITY OF TECHNOLOGY"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Eindhoven University of Technology, P.O. Box 513, NL-5600, MB, Eindhoven, The Netherlands","institution_ids":["https://openalex.org/I83019370"]},{"raw_affiliation_string":"EINDHOVEN UNIVERSITY OF TECHNOLOGY","institution_ids":["https://openalex.org/I83019370"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5011378033","display_name":"Bart Mesman","orcid":null},"institutions":[{"id":"https://openalex.org/I109147379","display_name":"NXP (Netherlands)","ror":"https://ror.org/059be4e97","country_code":"NL","type":"company","lineage":["https://openalex.org/I109147379"]},{"id":"https://openalex.org/I1329325741","display_name":"Philips (Finland)","ror":"https://ror.org/01g4jev56","country_code":"FI","type":"company","lineage":["https://openalex.org/I1329325741","https://openalex.org/I4210122849"]},{"id":"https://openalex.org/I4210153656","display_name":"Holst Centre (Netherlands)","ror":"https://ror.org/04abpa862","country_code":"NL","type":"company","lineage":["https://openalex.org/I4210153656"]},{"id":"https://openalex.org/I83019370","display_name":"Eindhoven University of Technology","ror":"https://ror.org/02c2kyt77","country_code":"NL","type":"education","lineage":["https://openalex.org/I83019370"]}],"countries":["FI","NL"],"is_corresponding":false,"raw_author_name":"Bart Mesman","raw_affiliation_strings":["Department of Electrical Engineering, Eindhoven University of Technology, P.O. Box 513, NL-5600, MB, Eindhoven, The Netherlands","Philips Research Laboratories, Eindhoven, Prof. Holstlaan 4, NL-5656, AA, Eindhoven, The Netherlands","Eindhoven University of Technology","Philips Research Laboratories Eindhoven"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Eindhoven University of Technology, P.O. Box 513, NL-5600, MB, Eindhoven, The Netherlands","institution_ids":["https://openalex.org/I83019370"]},{"raw_affiliation_string":"Philips Research Laboratories, Eindhoven, Prof. Holstlaan 4, NL-5656, AA, Eindhoven, The Netherlands","institution_ids":["https://openalex.org/I109147379","https://openalex.org/I1329325741","https://openalex.org/I4210153656"]},{"raw_affiliation_string":"Eindhoven University of Technology","institution_ids":["https://openalex.org/I83019370"]},{"raw_affiliation_string":"Philips Research Laboratories Eindhoven","institution_ids":["https://openalex.org/I1329325741"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5081768631","display_name":"Henk Corporaal","orcid":"https://orcid.org/0000-0003-4506-5732"},"institutions":[{"id":"https://openalex.org/I4210114974","display_name":"IMEC","ror":"https://ror.org/02kcbn207","country_code":"BE","type":"nonprofit","lineage":["https://openalex.org/I4210114974"]},{"id":"https://openalex.org/I83019370","display_name":"Eindhoven University of Technology","ror":"https://ror.org/02c2kyt77","country_code":"NL","type":"education","lineage":["https://openalex.org/I83019370"]}],"countries":["BE","NL"],"is_corresponding":false,"raw_author_name":"Henk Corporaal","raw_affiliation_strings":["Department of Electrical Engineering, Eindhoven University of Technology, P.O. Box 513, NL-5600, MB, Eindhoven, The Netherlands","IMEC, Kapeldreef 75, B-3001, Leuven, Belgium","Eindhoven University of Technology"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Eindhoven University of Technology, P.O. Box 513, NL-5600, MB, Eindhoven, The Netherlands","institution_ids":["https://openalex.org/I83019370"]},{"raw_affiliation_string":"IMEC, Kapeldreef 75, B-3001, Leuven, Belgium","institution_ids":["https://openalex.org/I4210114974"]},{"raw_affiliation_string":"Eindhoven University of Technology","institution_ids":["https://openalex.org/I83019370"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":{"value":5000,"currency":"EUR","value_usd":5392},"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"2","last_page":"16"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.9092742800712585},{"id":"https://openalex.org/keywords/register-file","display_name":"Register file","score":0.8198904991149902},{"id":"https://openalex.org/keywords/register-allocation","display_name":"Register allocation","score":0.6678271293640137},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.5894618034362793},{"id":"https://openalex.org/keywords/instruction-scheduling","display_name":"Instruction scheduling","score":0.5890401005744934},{"id":"https://openalex.org/keywords/code-generation","display_name":"Code generation","score":0.5847019553184509},{"id":"https://openalex.org/keywords/processor-register","display_name":"Processor register","score":0.5532276034355164},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5497919321060181},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.4959500730037689},{"id":"https://openalex.org/keywords/addressing-mode","display_name":"Addressing mode","score":0.472507119178772},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.4041929841041565},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.36747485399246216},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.2720821499824524},{"id":"https://openalex.org/keywords/instructions-per-cycle","display_name":"Instructions per cycle","score":0.2701307535171509},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.23218262195587158},{"id":"https://openalex.org/keywords/schedule","display_name":"Schedule","score":0.17469581961631775},{"id":"https://openalex.org/keywords/memory-address","display_name":"Memory address","score":0.16941162943840027},{"id":"https://openalex.org/keywords/dynamic-priority-scheduling","display_name":"Dynamic priority scheduling","score":0.11985325813293457},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.11428189277648926}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.9092742800712585},{"id":"https://openalex.org/C117280010","wikidata":"https://www.wikidata.org/wiki/Q180944","display_name":"Register file","level":3,"score":0.8198904991149902},{"id":"https://openalex.org/C128916667","wikidata":"https://www.wikidata.org/wiki/Q1343660","display_name":"Register allocation","level":3,"score":0.6678271293640137},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.5894618034362793},{"id":"https://openalex.org/C73564150","wikidata":"https://www.wikidata.org/wiki/Q11417093","display_name":"Instruction scheduling","level":5,"score":0.5890401005744934},{"id":"https://openalex.org/C133162039","wikidata":"https://www.wikidata.org/wiki/Q1061077","display_name":"Code generation","level":3,"score":0.5847019553184509},{"id":"https://openalex.org/C2871975","wikidata":"https://www.wikidata.org/wiki/Q187466","display_name":"Processor register","level":4,"score":0.5532276034355164},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5497919321060181},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.4959500730037689},{"id":"https://openalex.org/C16901944","wikidata":"https://www.wikidata.org/wiki/Q367183","display_name":"Addressing mode","level":4,"score":0.472507119178772},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.4041929841041565},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.36747485399246216},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.2720821499824524},{"id":"https://openalex.org/C156972235","wikidata":"https://www.wikidata.org/wiki/Q1443434","display_name":"Instructions per cycle","level":3,"score":0.2701307535171509},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.23218262195587158},{"id":"https://openalex.org/C68387754","wikidata":"https://www.wikidata.org/wiki/Q7271585","display_name":"Schedule","level":2,"score":0.17469581961631775},{"id":"https://openalex.org/C153247305","wikidata":"https://www.wikidata.org/wiki/Q835713","display_name":"Memory address","level":3,"score":0.16941162943840027},{"id":"https://openalex.org/C107568181","wikidata":"https://www.wikidata.org/wiki/Q5319000","display_name":"Dynamic priority scheduling","level":3,"score":0.11985325813293457},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.11428189277648926},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C49154492","wikidata":"https://www.wikidata.org/wiki/Q5300","display_name":"Central processing unit","level":2,"score":0.0},{"id":"https://openalex.org/C119948110","wikidata":"https://www.wikidata.org/wiki/Q7858726","display_name":"Two-level scheduling","level":4,"score":0.0},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1007/978-3-540-39920-9_2","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-540-39920-9_2","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},{"id":"pmh:oai:pure.tue.nl:openaire_cris_publications/c1d08cbd-b779-447e-84e2-3679fb9c20cc","is_oa":false,"landing_page_url":"https://research.tue.nl/en/publications/c1d08cbd-b779-447e-84e2-3679fb9c20cc","pdf_url":null,"source":{"id":"https://openalex.org/S4406922641","display_name":"TU/e Research Portal","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Zhao, Q, Mesman, B & Corporaal, H 2003, Limited address range architecture for reducing code size in embedded processors. in A Krall (ed.), Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Lecture Notes in Computer Science (LNCS), vol. 2826, Springer, pp. 2-16. https://doi.org/10.1007/978-3-540-39920-9_2","raw_type":"info:eu-repo/semantics/bookPart"},{"id":"pmh:oai:pure.tue.nl:publications/c1d08cbd-b779-447e-84e2-3679fb9c20cc","is_oa":false,"landing_page_url":"http://www.scopus.com/inward/record.url?scp=35248829590&partnerID=8YFLogxK","pdf_url":null,"source":{"id":"https://openalex.org/S4406922641","display_name":"TU/e Research Portal","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Zhao, Q, Mesman, B & Corporaal, H 2003, Limited address range architecture for reducing code size in embedded processors. in A Krall (ed.), Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). Lecture Notes in Computer Science (LNCS), vol. 2826, Springer, pp. 2-16. https://doi.org/10.1007/978-3-540-39920-9_2","raw_type":"info:eu-repo/semantics/bookPart"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W2040908559","https://openalex.org/W2095798192","https://openalex.org/W2112324761","https://openalex.org/W2125445813","https://openalex.org/W2162365056","https://openalex.org/W2166203884","https://openalex.org/W2539144973","https://openalex.org/W2543996155","https://openalex.org/W2576288252","https://openalex.org/W4242256571","https://openalex.org/W4253600508","https://openalex.org/W4256564450"],"related_works":["https://openalex.org/W2224192221","https://openalex.org/W3022691489","https://openalex.org/W2165125411","https://openalex.org/W2000718530","https://openalex.org/W2104554143","https://openalex.org/W2554856125","https://openalex.org/W2581286023","https://openalex.org/W2054117411","https://openalex.org/W1506246762","https://openalex.org/W2161016424"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2026-07-25T09:21:30.201066","created_date":"2025-10-10T00:00:00"}
