{"id":"https://openalex.org/W1870483643","doi":"https://doi.org/10.1007/978-3-540-39762-5_57","title":"A Practical ASIC Methodology for Flexible Clock Tree Synthesis with Routing Blockages","display_name":"A Practical ASIC Methodology for Flexible Clock Tree Synthesis with Routing Blockages","publication_year":2003,"publication_date":"2003-01-01","ids":{"openalex":"https://openalex.org/W1870483643","doi":"https://doi.org/10.1007/978-3-540-39762-5_57","mag":"1870483643"},"language":"en","primary_location":{"id":"doi:10.1007/978-3-540-39762-5_57","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-540-39762-5_57","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},"type":"book-chapter","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100450580","display_name":"Dongsheng Wang","orcid":"https://orcid.org/0000-0001-7676-7767"},"institutions":[{"id":"https://openalex.org/I4210156212","display_name":"Mentor Technologies","ror":"https://ror.org/05vewsj04","country_code":"US","type":"other","lineage":["https://openalex.org/I4210156212"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Dongsheng Wang","raw_affiliation_strings":["Mentor Graphics Corporation, 8005 S.W. Boeckman Road, Wilsonville, Oregon, 97070, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Mentor Graphics Corporation, 8005 S.W. Boeckman Road, Wilsonville, Oregon, 97070, USA","institution_ids":["https://openalex.org/I4210156212"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063606966","display_name":"Peter Suaris","orcid":null},"institutions":[{"id":"https://openalex.org/I4210156212","display_name":"Mentor Technologies","ror":"https://ror.org/05vewsj04","country_code":"US","type":"other","lineage":["https://openalex.org/I4210156212"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Peter Suaris","raw_affiliation_strings":["Mentor Graphics Corporation, 8005 S.W. Boeckman Road, Wilsonville, Oregon, 97070, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Mentor Graphics Corporation, 8005 S.W. Boeckman Road, Wilsonville, Oregon, 97070, USA","institution_ids":["https://openalex.org/I4210156212"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5060536841","display_name":"Nan-Chi Chou","orcid":null},"institutions":[{"id":"https://openalex.org/I4210156212","display_name":"Mentor Technologies","ror":"https://ror.org/05vewsj04","country_code":"US","type":"other","lineage":["https://openalex.org/I4210156212"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nan-chi Chou","raw_affiliation_strings":["Mentor Graphics Corporation, 8005 S.W. Boeckman Road, Wilsonville, Oregon, 97070, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Mentor Graphics Corporation, 8005 S.W. Boeckman Road, Wilsonville, Oregon, 97070, USA","institution_ids":["https://openalex.org/I4210156212"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I4210156212"],"apc_list":{"value":5000,"currency":"EUR","value_usd":5392},"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.18172129,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":95,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"511","last_page":"519"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7730840444564819},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.6421436667442322},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.5800737738609314},{"id":"https://openalex.org/keywords/clock-drift","display_name":"Clock drift","score":0.5709205865859985},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5616018176078796},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.5585654377937317},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.5333870053291321},{"id":"https://openalex.org/keywords/tree","display_name":"Tree (set theory)","score":0.5307920575141907},{"id":"https://openalex.org/keywords/clock-network","display_name":"Clock network","score":0.5287489295005798},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.5158388018608093},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.512267529964447},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.49915575981140137},{"id":"https://openalex.org/keywords/macro","display_name":"Macro","score":0.4806024730205536},{"id":"https://openalex.org/keywords/vector-clock","display_name":"Vector clock","score":0.46780088543891907},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.4612056612968445},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.4581034183502197},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.4417508542537689},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.38557347655296326},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.3464333415031433},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.11189478635787964},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.105246901512146},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.06911259889602661},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.0611555278301239}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7730840444564819},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.6421436667442322},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.5800737738609314},{"id":"https://openalex.org/C155837451","wikidata":"https://www.wikidata.org/wiki/Q1069144","display_name":"Clock drift","level":5,"score":0.5709205865859985},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5616018176078796},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.5585654377937317},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.5333870053291321},{"id":"https://openalex.org/C113174947","wikidata":"https://www.wikidata.org/wiki/Q2859736","display_name":"Tree (set theory)","level":2,"score":0.5307920575141907},{"id":"https://openalex.org/C2778182565","wikidata":"https://www.wikidata.org/wiki/Q1752879","display_name":"Clock network","level":5,"score":0.5287489295005798},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.5158388018608093},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.512267529964447},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.49915575981140137},{"id":"https://openalex.org/C166955791","wikidata":"https://www.wikidata.org/wiki/Q629579","display_name":"Macro","level":2,"score":0.4806024730205536},{"id":"https://openalex.org/C52563298","wikidata":"https://www.wikidata.org/wiki/Q1413349","display_name":"Vector clock","level":5,"score":0.46780088543891907},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.4612056612968445},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.4581034183502197},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.4417508542537689},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.38557347655296326},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.3464333415031433},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.11189478635787964},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.105246901512146},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.06911259889602661},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0611555278301239},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/978-3-540-39762-5_57","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-540-39762-5_57","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1992904457","https://openalex.org/W1997263601","https://openalex.org/W2023981464","https://openalex.org/W2068670364","https://openalex.org/W2100928338","https://openalex.org/W2103015023","https://openalex.org/W2136630977","https://openalex.org/W2138817962","https://openalex.org/W2140367260","https://openalex.org/W2148203223","https://openalex.org/W2148609278","https://openalex.org/W2159866772","https://openalex.org/W3150437273","https://openalex.org/W3154674285","https://openalex.org/W4237096326","https://openalex.org/W4248546709"],"related_works":["https://openalex.org/W2292909929","https://openalex.org/W1497331638","https://openalex.org/W2246178160","https://openalex.org/W2787237207","https://openalex.org/W2617666058","https://openalex.org/W2411759562","https://openalex.org/W2116021798","https://openalex.org/W2520965597","https://openalex.org/W3048124756","https://openalex.org/W2015870461"],"abstract_inverted_index":null,"counts_by_year":[{"year":2026,"cited_by_count":1}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}
