{"id":"https://openalex.org/W1541735515","doi":"https://doi.org/10.1007/978-3-540-39762-5_2","title":"Analysis of High-Speed Logic Families","display_name":"Analysis of High-Speed Logic Families","publication_year":2003,"publication_date":"2003-01-01","ids":{"openalex":"https://openalex.org/W1541735515","doi":"https://doi.org/10.1007/978-3-540-39762-5_2","mag":"1541735515"},"language":"en","primary_location":{"id":"doi:10.1007/978-3-540-39762-5_2","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-540-39762-5_2","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},"type":"book-chapter","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5054728951","display_name":"Giovanni Privitera","orcid":null},"institutions":[{"id":"https://openalex.org/I4210122849","display_name":"Philips (Netherlands)","ror":"https://ror.org/02p2bgp27","country_code":"NL","type":"company","lineage":["https://openalex.org/I4210122849"]}],"countries":["NL"],"is_corresponding":true,"raw_author_name":"G. Privitera","raw_affiliation_strings":["Philips Research, Prof. Holstlaan 4, 5656 AA, Eindhoven, The Netherlands"],"affiliations":[{"raw_affiliation_string":"Philips Research, Prof. Holstlaan 4, 5656 AA, Eindhoven, The Netherlands","institution_ids":["https://openalex.org/I4210122849"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5085927985","display_name":"F. Pessolano","orcid":null},"institutions":[{"id":"https://openalex.org/I4210122849","display_name":"Philips (Netherlands)","ror":"https://ror.org/02p2bgp27","country_code":"NL","type":"company","lineage":["https://openalex.org/I4210122849"]}],"countries":["NL"],"is_corresponding":false,"raw_author_name":"Francesco Pessolano","raw_affiliation_strings":["Philips Research, Prof. Holstlaan 4, 5656 AA, Eindhoven, The Netherlands"],"affiliations":[{"raw_affiliation_string":"Philips Research, Prof. Holstlaan 4, 5656 AA, Eindhoven, The Netherlands","institution_ids":["https://openalex.org/I4210122849"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5054728951"],"corresponding_institution_ids":["https://openalex.org/I4210122849"],"apc_list":{"value":5000,"currency":"EUR","value_usd":5392},"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.15065212,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"2","last_page":"10"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/domino-logic","display_name":"Domino logic","score":0.7416195869445801},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.6560662984848022},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.5748768448829651},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5694248080253601},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.5576580762863159},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.510454535484314},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.48936814069747925},{"id":"https://openalex.org/keywords/dynamic-logic","display_name":"Dynamic logic (digital electronics)","score":0.47873684763908386},{"id":"https://openalex.org/keywords/current-mode-logic","display_name":"Current-mode logic","score":0.46186453104019165},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.41821953654289246},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.3573237359523773},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.28256088495254517},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.23935094475746155},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.20771369338035583},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.20628958940505981},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19471031427383423},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.1258316934108734},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.08695679903030396},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.07265782356262207}],"concepts":[{"id":"https://openalex.org/C2777555262","wikidata":"https://www.wikidata.org/wiki/Q173391","display_name":"Domino logic","level":5,"score":0.7416195869445801},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.6560662984848022},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.5748768448829651},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5694248080253601},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.5576580762863159},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.510454535484314},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.48936814069747925},{"id":"https://openalex.org/C2777796570","wikidata":"https://www.wikidata.org/wiki/Q2351326","display_name":"Dynamic logic (digital electronics)","level":4,"score":0.47873684763908386},{"id":"https://openalex.org/C2780295579","wikidata":"https://www.wikidata.org/wiki/Q5195108","display_name":"Current-mode logic","level":3,"score":0.46186453104019165},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.41821953654289246},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.3573237359523773},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.28256088495254517},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.23935094475746155},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.20771369338035583},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.20628958940505981},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19471031427383423},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.1258316934108734},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.08695679903030396},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.07265782356262207}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/978-3-540-39762-5_2","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-540-39762-5_2","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1491093261","https://openalex.org/W2102653533","https://openalex.org/W2116987876","https://openalex.org/W2133918365","https://openalex.org/W2136899384","https://openalex.org/W2149009819","https://openalex.org/W2155199871","https://openalex.org/W2168843308","https://openalex.org/W2250104225","https://openalex.org/W4212961314"],"related_works":["https://openalex.org/W2991771859","https://openalex.org/W2993752723","https://openalex.org/W3042080464","https://openalex.org/W2155174752","https://openalex.org/W2802423915","https://openalex.org/W2118487491","https://openalex.org/W3122224509","https://openalex.org/W2158157809","https://openalex.org/W321873635","https://openalex.org/W1601832081"],"abstract_inverted_index":null,"counts_by_year":[{"year":2023,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
