{"id":"https://openalex.org/W135206478","doi":"https://doi.org/10.1007/978-3-540-30205-6_47","title":"Wirelength Reduction Using 3-D Physical Design","display_name":"Wirelength Reduction Using 3-D Physical Design","publication_year":2004,"publication_date":"2004-01-01","ids":{"openalex":"https://openalex.org/W135206478","doi":"https://doi.org/10.1007/978-3-540-30205-6_47","mag":"135206478"},"language":"en","primary_location":{"id":"doi:10.1007/978-3-540-30205-6_47","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-540-30205-6_47","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},"type":"book-chapter","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5074559088","display_name":"Idris Kaya","orcid":null},"institutions":[{"id":"https://openalex.org/I114112103","display_name":"Leibniz University Hannover","ror":"https://ror.org/0304hq317","country_code":"DE","type":"education","lineage":["https://openalex.org/I114112103"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Idris Kaya","raw_affiliation_strings":["Institute of Microelectronic Systems, University of Hannover, Appelstr. 4, 30167, Hannover, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Microelectronic Systems, University of Hannover, Appelstr. 4, 30167, Hannover, Germany","institution_ids":["https://openalex.org/I114112103"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5086621046","display_name":"Silke Salewski","orcid":null},"institutions":[{"id":"https://openalex.org/I114112103","display_name":"Leibniz University Hannover","ror":"https://ror.org/0304hq317","country_code":"DE","type":"education","lineage":["https://openalex.org/I114112103"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Silke Salewski","raw_affiliation_strings":["Institute of Microelectronic Systems, University of Hannover, Appelstr. 4, 30167, Hannover, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Microelectronic Systems, University of Hannover, Appelstr. 4, 30167, Hannover, Germany","institution_ids":["https://openalex.org/I114112103"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010238994","display_name":"Markus Olbrich","orcid":"https://orcid.org/0000-0001-9851-5982"},"institutions":[{"id":"https://openalex.org/I114112103","display_name":"Leibniz University Hannover","ror":"https://ror.org/0304hq317","country_code":"DE","type":"education","lineage":["https://openalex.org/I114112103"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Markus Olbrich","raw_affiliation_strings":["Institute of Microelectronic Systems, University of Hannover, Appelstr. 4, 30167, Hannover, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Microelectronic Systems, University of Hannover, Appelstr. 4, 30167, Hannover, Germany","institution_ids":["https://openalex.org/I114112103"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5057367287","display_name":"Erich Barke","orcid":"https://orcid.org/0000-0001-5744-2940"},"institutions":[{"id":"https://openalex.org/I114112103","display_name":"Leibniz University Hannover","ror":"https://ror.org/0304hq317","country_code":"DE","type":"education","lineage":["https://openalex.org/I114112103"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Erich Barke","raw_affiliation_strings":["Institute of Microelectronic Systems, University of Hannover, Appelstr. 4, 30167, Hannover, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Microelectronic Systems, University of Hannover, Appelstr. 4, 30167, Hannover, Germany","institution_ids":["https://openalex.org/I114112103"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":{"value":5000,"currency":"EUR","value_usd":5392},"apc_paid":null,"fwci":3.8048,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.91307293,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"453","last_page":"462"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9851999878883362,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.8620468378067017},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.7274397015571594},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.718140184879303},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.7084393501281738},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.6537549495697021},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.5633774995803833},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5405283570289612},{"id":"https://openalex.org/keywords/placement","display_name":"Placement","score":0.49453088641166687},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.4766952693462372},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4625866115093231},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4604400396347046},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.42465871572494507},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.41645359992980957},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3585057258605957},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.3458201289176941},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.33275365829467773},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.2900821566581726},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2531472444534302},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.22346842288970947},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.11682388186454773},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09176215529441833}],"concepts":[{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.8620468378067017},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.7274397015571594},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.718140184879303},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.7084393501281738},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.6537549495697021},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.5633774995803833},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5405283570289612},{"id":"https://openalex.org/C117690923","wikidata":"https://www.wikidata.org/wiki/Q1484784","display_name":"Placement","level":4,"score":0.49453088641166687},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.4766952693462372},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4625866115093231},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4604400396347046},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.42465871572494507},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.41645359992980957},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3585057258605957},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.3458201289176941},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.33275365829467773},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.2900821566581726},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2531472444534302},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.22346842288970947},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.11682388186454773},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09176215529441833},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/978-3-540-30205-6_47","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-540-30205-6_47","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.7799999713897705,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1497256448","https://openalex.org/W1871592703","https://openalex.org/W2002041333","https://openalex.org/W2048796234","https://openalex.org/W2094042791","https://openalex.org/W2096042906","https://openalex.org/W2099297205","https://openalex.org/W2100611186","https://openalex.org/W2107166889","https://openalex.org/W2114542420","https://openalex.org/W2118390028","https://openalex.org/W2127012874","https://openalex.org/W2133863299","https://openalex.org/W2138401961","https://openalex.org/W2144149750","https://openalex.org/W2148777220","https://openalex.org/W2151340921","https://openalex.org/W2156771075","https://openalex.org/W2157558963","https://openalex.org/W4239055271","https://openalex.org/W4256007160"],"related_works":["https://openalex.org/W2781601456","https://openalex.org/W2115502122","https://openalex.org/W4211105560","https://openalex.org/W4249576260","https://openalex.org/W2001838379","https://openalex.org/W1974073956","https://openalex.org/W4230348337","https://openalex.org/W1525696892","https://openalex.org/W2353155791","https://openalex.org/W2138401961"],"abstract_inverted_index":null,"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}