{"id":"https://openalex.org/W1560143599","doi":"https://doi.org/10.1007/978-3-540-30117-2_93","title":"System-Level Modeling of Dynamically Reconfigurable Co-processors","display_name":"System-Level Modeling of Dynamically Reconfigurable Co-processors","publication_year":2004,"publication_date":"2004-01-01","ids":{"openalex":"https://openalex.org/W1560143599","doi":"https://doi.org/10.1007/978-3-540-30117-2_93","mag":"1560143599"},"language":"en","primary_location":{"id":"doi:10.1007/978-3-540-30117-2_93","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-540-30117-2_93","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101494498","display_name":"Yang Qu","orcid":"https://orcid.org/0000-0001-7909-4107"},"institutions":[{"id":"https://openalex.org/I87653560","display_name":"VTT Technical Research Centre of Finland","ror":"https://ror.org/04b181w54","country_code":"FI","type":"nonprofit","lineage":["https://openalex.org/I4210089493","https://openalex.org/I87653560"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"Yang Qu","raw_affiliation_strings":["VTT Electronics, P.O. Box 1100, (Kaitov\u00e4yl\u00e4 1), FIN-90571, Oulu, Finland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"VTT Electronics, P.O. Box 1100, (Kaitov\u00e4yl\u00e4 1), FIN-90571, Oulu, Finland","institution_ids":["https://openalex.org/I87653560"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087798619","display_name":"Kari Tiensyrj\u00e4","orcid":null},"institutions":[{"id":"https://openalex.org/I87653560","display_name":"VTT Technical Research Centre of Finland","ror":"https://ror.org/04b181w54","country_code":"FI","type":"nonprofit","lineage":["https://openalex.org/I4210089493","https://openalex.org/I87653560"]}],"countries":["FI"],"is_corresponding":false,"raw_author_name":"Kari Tiensyrj\u00e4","raw_affiliation_strings":["VTT Electronics, P.O. Box 1100, (Kaitov\u00e4yl\u00e4 1), FIN-90571, Oulu, Finland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"VTT Electronics, P.O. Box 1100, (Kaitov\u00e4yl\u00e4 1), FIN-90571, Oulu, Finland","institution_ids":["https://openalex.org/I87653560"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108075591","display_name":"K. Masselos","orcid":null},"institutions":[{"id":"https://openalex.org/I86100027","display_name":"Intracom Telecom (Greece)","ror":"https://ror.org/04npy5k94","country_code":"GR","type":"company","lineage":["https://openalex.org/I86100027"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Kostas Masselos","raw_affiliation_strings":["Emerging Technologies and Markets Division, INTRACOM SA, 19,5km Markopoulou Avenue, P.O.Box 68, GR 19002, Peania, Attika, Greece"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Emerging Technologies and Markets Division, INTRACOM SA, 19,5km Markopoulou Avenue, P.O.Box 68, GR 19002, Peania, Attika, Greece","institution_ids":["https://openalex.org/I86100027"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":{"value":5000,"currency":"EUR","value_usd":5392},"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":14,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"881","last_page":"885"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/systemc","display_name":"SystemC","score":0.9178897738456726},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.8979184627532959},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.777481734752655},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.6776904463768005},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6423066854476929},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6380603909492493},{"id":"https://openalex.org/keywords/electronic-system-level-design-and-verification","display_name":"Electronic system-level design and verification","score":0.6361292600631714},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.5357564687728882},{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.5295839309692383},{"id":"https://openalex.org/keywords/systems-design","display_name":"Systems design","score":0.4182559847831726},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.4011552631855011},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.35817021131515503},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.1301906704902649}],"concepts":[{"id":"https://openalex.org/C2776928060","wikidata":"https://www.wikidata.org/wiki/Q1753563","display_name":"SystemC","level":2,"score":0.9178897738456726},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.8979184627532959},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.777481734752655},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.6776904463768005},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6423066854476929},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6380603909492493},{"id":"https://openalex.org/C77495112","wikidata":"https://www.wikidata.org/wiki/Q5358436","display_name":"Electronic system-level design and verification","level":2,"score":0.6361292600631714},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.5357564687728882},{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.5295839309692383},{"id":"https://openalex.org/C31352089","wikidata":"https://www.wikidata.org/wiki/Q3750474","display_name":"Systems design","level":2,"score":0.4182559847831726},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.4011552631855011},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.35817021131515503},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.1301906704902649},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/978-3-540-30117-2_93","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-540-30117-2_93","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1975051142","https://openalex.org/W2066868843","https://openalex.org/W2117796172","https://openalex.org/W2119501389","https://openalex.org/W2127267120","https://openalex.org/W2155481891","https://openalex.org/W3137064961"],"related_works":["https://openalex.org/W2790192245","https://openalex.org/W1831349210","https://openalex.org/W2059569687","https://openalex.org/W3206586607","https://openalex.org/W1996984607","https://openalex.org/W2975035977","https://openalex.org/W2159088510","https://openalex.org/W2046352736","https://openalex.org/W2170029576","https://openalex.org/W2548514518"],"abstract_inverted_index":null,"counts_by_year":[{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}