{"id":"https://openalex.org/W1548553328","doi":"https://doi.org/10.1007/978-3-540-24677-0_61","title":"A Comparison of Two Circuit Representations for Evolutionary Digital Circuit Design","display_name":"A Comparison of Two Circuit Representations for Evolutionary Digital Circuit Design","publication_year":2004,"publication_date":"2004-01-01","ids":{"openalex":"https://openalex.org/W1548553328","doi":"https://doi.org/10.1007/978-3-540-24677-0_61","mag":"1548553328"},"language":"en","primary_location":{"id":"doi:10.1007/978-3-540-24677-0_61","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-540-24677-0_61","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},"type":"book","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://researchonline.federation.edu.au/vital/access/HandleResolver/1959.17/43613","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5084920912","display_name":"Nadia Nedjah","orcid":"https://orcid.org/0000-0002-1656-6397"},"institutions":[{"id":"https://openalex.org/I40034438","display_name":"Universidade do Estado do Rio de Janeiro","ror":"https://ror.org/0198v2949","country_code":"BR","type":"education","lineage":["https://openalex.org/I40034438"]}],"countries":["BR"],"is_corresponding":true,"raw_author_name":"Nadia Nedjah","raw_affiliation_strings":["Department of Systems Engineering and Computation, Faculty of Engineering, State University of Rio de Janeiro, Rio de Janeiro, Brazil"],"affiliations":[{"raw_affiliation_string":"Department of Systems Engineering and Computation, Faculty of Engineering, State University of Rio de Janeiro, Rio de Janeiro, Brazil","institution_ids":["https://openalex.org/I40034438"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5048916912","display_name":"Luiza de Macedo Mourelle","orcid":"https://orcid.org/0000-0002-4680-2047"},"institutions":[{"id":"https://openalex.org/I40034438","display_name":"Universidade do Estado do Rio de Janeiro","ror":"https://ror.org/0198v2949","country_code":"BR","type":"education","lineage":["https://openalex.org/I40034438"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"Luiza de Macedo Mourelle","raw_affiliation_strings":["Department of Systems Engineering and Computation, Faculty of Engineering, State University of Rio de Janeiro, Rio de Janeiro, Brazil"],"affiliations":[{"raw_affiliation_string":"Department of Systems Engineering and Computation, Faculty of Engineering, State University of Rio de Janeiro, Rio de Janeiro, Brazil","institution_ids":["https://openalex.org/I40034438"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5084920912"],"corresponding_institution_ids":["https://openalex.org/I40034438"],"apc_list":{"value":5000,"currency":"EUR","value_usd":5392},"apc_paid":null,"fwci":0.2275,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.524708,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"594","last_page":"604"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11975","display_name":"Evolutionary Algorithms and Applications","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11975","display_name":"Evolutionary Algorithms and Applications","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10100","display_name":"Metaheuristic Optimization Algorithms Research","score":0.9769999980926514,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11764","display_name":"Evolution and Genetic Dynamics","score":0.9438999891281128,"subfield":{"id":"https://openalex.org/subfields/1311","display_name":"Genetics"},"field":{"id":"https://openalex.org/fields/13","display_name":"Biochemistry, Genetics and Molecular Biology"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8138442635536194},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.6935564279556274},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.6744964122772217},{"id":"https://openalex.org/keywords/encoding","display_name":"Encoding (memory)","score":0.5868678689002991},{"id":"https://openalex.org/keywords/genetic-programming","display_name":"Genetic programming","score":0.5220315456390381},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4900614023208618},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.48593869805336},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.4608663022518158},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.449594646692276},{"id":"https://openalex.org/keywords/mixed-signal-integrated-circuit","display_name":"Mixed-signal integrated circuit","score":0.4488997459411621},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.415999174118042},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3962319791316986},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.3748834431171417},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.2564706802368164},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.20824766159057617},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.14422297477722168},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10127976536750793},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.09674659371376038},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.08757582306861877},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.0867449939250946},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.07022249698638916}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8138442635536194},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.6935564279556274},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.6744964122772217},{"id":"https://openalex.org/C125411270","wikidata":"https://www.wikidata.org/wiki/Q18653","display_name":"Encoding (memory)","level":2,"score":0.5868678689002991},{"id":"https://openalex.org/C110332635","wikidata":"https://www.wikidata.org/wiki/Q629498","display_name":"Genetic programming","level":2,"score":0.5220315456390381},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4900614023208618},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.48593869805336},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.4608663022518158},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.449594646692276},{"id":"https://openalex.org/C62907940","wikidata":"https://www.wikidata.org/wiki/Q1541329","display_name":"Mixed-signal integrated circuit","level":3,"score":0.4488997459411621},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.415999174118042},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3962319791316986},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.3748834431171417},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.2564706802368164},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.20824766159057617},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.14422297477722168},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10127976536750793},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.09674659371376038},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.08757582306861877},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0867449939250946},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.07022249698638916},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1007/978-3-540-24677-0_61","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-540-24677-0_61","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},{"id":"mag:1548553328","is_oa":true,"landing_page_url":"http://researchonline.federation.edu.au/vital/access/HandleResolver/1959.17/43613","pdf_url":null,"source":{"id":"https://openalex.org/S4306400234","display_name":"FedUni ResearchOnline (Federation University Australia)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210158496","host_organization_name":"Australian Federation of University Women \u2013 South Australia","host_organization_lineage":["https://openalex.org/I4210158496"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"FedUni ResearchOnline (Federation University Australia)","raw_type":null}],"best_oa_location":{"id":"mag:1548553328","is_oa":true,"landing_page_url":"http://researchonline.federation.edu.au/vital/access/HandleResolver/1959.17/43613","pdf_url":null,"source":{"id":"https://openalex.org/S4306400234","display_name":"FedUni ResearchOnline (Federation University Australia)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210158496","host_organization_name":"Australian Federation of University Women \u2013 South Australia","host_organization_lineage":["https://openalex.org/I4210158496"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"FedUni ResearchOnline (Federation University Australia)","raw_type":null},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W1555776675","https://openalex.org/W2083294917","https://openalex.org/W2169842631","https://openalex.org/W3157409424"],"related_works":["https://openalex.org/W2929481550","https://openalex.org/W2836185852","https://openalex.org/W2820054223","https://openalex.org/W2825607828","https://openalex.org/W2849279782","https://openalex.org/W2846564819","https://openalex.org/W2845350670","https://openalex.org/W2870014154"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
