{"id":"https://openalex.org/W2965646120","doi":"https://doi.org/10.1007/978-3-322-95233-2_19","title":"A Hierarchy Preserving Hierarchical Bottom-Up 2-layer Wiring Algorithm with Respect to Via Minimization","display_name":"A Hierarchy Preserving Hierarchical Bottom-Up 2-layer Wiring Algorithm with Respect to Via Minimization","publication_year":1992,"publication_date":"1992-01-01","ids":{"openalex":"https://openalex.org/W2965646120","doi":"https://doi.org/10.1007/978-3-322-95233-2_19","mag":"2965646120"},"language":"en","primary_location":{"id":"doi:10.1007/978-3-322-95233-2_19","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-322-95233-2_19","pdf_url":null,"source":{"id":"https://openalex.org/S4210233246","display_name":"Teubner-Texte zur Informatik","issn_l":"1615-4584","issn":["1615-4584"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"TEUBNER-TEXTE zur Informatik","raw_type":"book-chapter"},"type":"book-chapter","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5007586603","display_name":"Paul Molitor","orcid":"https://orcid.org/0000-0003-1461-7936"},"institutions":[{"id":"https://openalex.org/I91712215","display_name":"Saarland University","ror":"https://ror.org/01jdpyv68","country_code":"DE","type":"education","lineage":["https://openalex.org/I91712215"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Paul Molitor","raw_affiliation_strings":["Fachbereich 14 - Informatik, Universit\u00e4t des Saarlandes, 6600, Saarbr\u00fccken, Germany"],"affiliations":[{"raw_affiliation_string":"Fachbereich 14 - Informatik, Universit\u00e4t des Saarlandes, 6600, Saarbr\u00fccken, Germany","institution_ids":["https://openalex.org/I91712215"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5007586603"],"corresponding_institution_ids":["https://openalex.org/I91712215"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.46533128,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"333","last_page":"348"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/hierarchy","display_name":"Hierarchy","score":0.8252840042114258},{"id":"https://openalex.org/keywords/minification","display_name":"Minification","score":0.6996634006500244},{"id":"https://openalex.org/keywords/layer","display_name":"Layer (electronics)","score":0.6638404726982117},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.5913252830505371},{"id":"https://openalex.org/keywords/hierarchical-control-system","display_name":"Hierarchical control system","score":0.5541964769363403},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5190204381942749},{"id":"https://openalex.org/keywords/connection","display_name":"Connection (principal bundle)","score":0.4573262929916382},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.42842021584510803},{"id":"https://openalex.org/keywords/circuit-complexity","display_name":"Circuit complexity","score":0.41026151180267334},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.4062168002128601},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.37130069732666016},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.32176148891448975},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2710873484611511},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.24799561500549316},{"id":"https://openalex.org/keywords/combinatorics","display_name":"Combinatorics","score":0.14809808135032654},{"id":"https://openalex.org/keywords/nanotechnology","display_name":"Nanotechnology","score":0.12511953711509705},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.11799398064613342},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.0957496166229248},{"id":"https://openalex.org/keywords/geometry","display_name":"Geometry","score":0.07516399025917053},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.06298667192459106}],"concepts":[{"id":"https://openalex.org/C31170391","wikidata":"https://www.wikidata.org/wiki/Q188619","display_name":"Hierarchy","level":2,"score":0.8252840042114258},{"id":"https://openalex.org/C147764199","wikidata":"https://www.wikidata.org/wiki/Q6865248","display_name":"Minification","level":2,"score":0.6996634006500244},{"id":"https://openalex.org/C2779227376","wikidata":"https://www.wikidata.org/wiki/Q6505497","display_name":"Layer (electronics)","level":2,"score":0.6638404726982117},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.5913252830505371},{"id":"https://openalex.org/C124527596","wikidata":"https://www.wikidata.org/wiki/Q17029359","display_name":"Hierarchical control system","level":3,"score":0.5541964769363403},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5190204381942749},{"id":"https://openalex.org/C13355873","wikidata":"https://www.wikidata.org/wiki/Q2920850","display_name":"Connection (principal bundle)","level":2,"score":0.4573262929916382},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.42842021584510803},{"id":"https://openalex.org/C90702460","wikidata":"https://www.wikidata.org/wiki/Q1055112","display_name":"Circuit complexity","level":3,"score":0.41026151180267334},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.4062168002128601},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.37130069732666016},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.32176148891448975},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2710873484611511},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.24799561500549316},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.14809808135032654},{"id":"https://openalex.org/C171250308","wikidata":"https://www.wikidata.org/wiki/Q11468","display_name":"Nanotechnology","level":1,"score":0.12511953711509705},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.11799398064613342},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0957496166229248},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.07516399025917053},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.06298667192459106},{"id":"https://openalex.org/C2775924081","wikidata":"https://www.wikidata.org/wiki/Q55608371","display_name":"Control (management)","level":2,"score":0.0},{"id":"https://openalex.org/C34447519","wikidata":"https://www.wikidata.org/wiki/Q179522","display_name":"Market economy","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/978-3-322-95233-2_19","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-322-95233-2_19","pdf_url":null,"source":{"id":"https://openalex.org/S4210233246","display_name":"Teubner-Texte zur Informatik","issn_l":"1615-4584","issn":["1615-4584"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"TEUBNER-TEXTE zur Informatik","raw_type":"book-chapter"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W150512894","https://openalex.org/W574066314","https://openalex.org/W1992980835","https://openalex.org/W2427045451","https://openalex.org/W2496556858","https://openalex.org/W3162191029","https://openalex.org/W6600498180","https://openalex.org/W6631263572","https://openalex.org/W6646416932","https://openalex.org/W6671607239"],"related_works":["https://openalex.org/W1895405313","https://openalex.org/W2167940021","https://openalex.org/W2942485139","https://openalex.org/W573714618","https://openalex.org/W2910225356","https://openalex.org/W2378192825","https://openalex.org/W2071815174","https://openalex.org/W4232598318","https://openalex.org/W2007455779","https://openalex.org/W2164371879"],"abstract_inverted_index":{"Here,":[0],"the":[1,37,45,48,55,60,82,115,119,126,131,134,139,157,160],"following":[2],"hierarchical":[3,69,100,161],"constrained":[4],"via":[5],"minimization":[6],"problem":[7,64,108],"(HCVM)":[8],"is":[9,50,73,92,110,150,156],"examined:":[10],"\u201cLet":[11],"Q":[12,26,58],"be":[13],"a":[14,17,22,29,99],"circuit":[15],"with":[16,34,68],"given":[18,114],"layout":[19],"hierarchy.":[20],"Find":[21],"2-layer":[23,61,116,136],"wiring":[24,137],"of":[25,31,39,47,57,84,90,118,121,133,138,141,159,163],"which":[27,72,109],"needs":[28],"number":[30],"vias":[32],"minimal":[33],"respect":[35],"to":[36,103],"preservation":[38],"hierarchy,":[40],"i.e.,":[41,113],"on":[42],"condition":[43],"that":[44],"description":[46,56,162],"result":[49],"(nearly)":[51],"as":[52,54],"short":[53],"before":[59],"wiring\u201d.":[62],"The":[63,87,146],"arises":[65],"in":[66],"connection":[67],"physical":[70],"synthesis,":[71],"not":[74],"highly":[75],"developed":[76],"yet":[77],"although":[78],"absolutely":[79],"essential":[80],"for":[81],"design":[83],"ULSI":[85],"circuits.":[86],"computational":[88],"complexity":[89],"HCVM":[91],"unknown":[93],"till":[94],"today.":[95],"This":[96],"paper":[97],"presents":[98],"bottom-up":[101],"algorithm":[102],"(a":[104],"variant":[105],"of)":[106],"this":[107],"locally":[111],"optimal,":[112],"wirings":[117,132],"subcircuits":[120],"level":[122,142],"i,":[123],"it":[124],"computes":[125],"optimal":[127],"(partially":[128],"induced":[129],"by":[130],"subcircuits)":[135],"circuits":[140],"i":[143],"+":[144],"1.":[145],"algorithm\u2019s":[147],"running":[148],"time":[149],"O(n":[151],"3":[152],")":[153],"where":[154],"n":[155],"size":[158],"Q.":[164]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}