{"id":"https://openalex.org/W2277859128","doi":"https://doi.org/10.1007/978-3-319-24369-6_32","title":"Designing of Hierarchical Structures for Binary Comparators on FPGA/SoC","display_name":"Designing of Hierarchical Structures for Binary Comparators on FPGA/SoC","publication_year":2015,"publication_date":"2015-01-01","ids":{"openalex":"https://openalex.org/W2277859128","doi":"https://doi.org/10.1007/978-3-319-24369-6_32","mag":"2277859128"},"language":"en","primary_location":{"id":"doi:10.1007/978-3-319-24369-6_32","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-319-24369-6_32","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},"type":"book-chapter","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"gold","oa_url":"https://inria.hal.science/hal-01444482","any_repository_has_fulltext":null},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5072900576","display_name":"Valery Salauyou","orcid":"https://orcid.org/0000-0002-9174-8588"},"institutions":[{"id":"https://openalex.org/I1323121030","display_name":"Bialystok University of Technology","ror":"https://ror.org/02bzfsy61","country_code":"PL","type":"education","lineage":["https://openalex.org/I1323121030"]}],"countries":["PL"],"is_corresponding":true,"raw_author_name":"Valery Salauyou","raw_affiliation_strings":["Faculty of Computer Science, Bialystok University of Technology, Bialystok, Poland"],"affiliations":[{"raw_affiliation_string":"Faculty of Computer Science, Bialystok University of Technology, Bialystok, Poland","institution_ids":["https://openalex.org/I1323121030"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5045810683","display_name":"Marek Gruszewski","orcid":null},"institutions":[{"id":"https://openalex.org/I1323121030","display_name":"Bialystok University of Technology","ror":"https://ror.org/02bzfsy61","country_code":"PL","type":"education","lineage":["https://openalex.org/I1323121030"]}],"countries":["PL"],"is_corresponding":false,"raw_author_name":"Marek Gruszewski","raw_affiliation_strings":["Faculty of Computer Science, Bialystok University of Technology, Bialystok, Poland"],"affiliations":[{"raw_affiliation_string":"Faculty of Computer Science, Bialystok University of Technology, Bialystok, Poland","institution_ids":["https://openalex.org/I1323121030"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5072900576"],"corresponding_institution_ids":["https://openalex.org/I1323121030"],"apc_list":{"value":5000,"currency":"EUR","value_usd":5392},"apc_paid":{"value":5000,"currency":"EUR","value_usd":5392},"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.14835681,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"386","last_page":"396"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.989799976348877,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/comparator","display_name":"Comparator","score":0.947304368019104},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8015297055244446},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6864755749702454},{"id":"https://openalex.org/keywords/binary-tree","display_name":"Binary tree","score":0.6446885466575623},{"id":"https://openalex.org/keywords/binary-number","display_name":"Binary number","score":0.6086040735244751},{"id":"https://openalex.org/keywords/tree","display_name":"Tree (set theory)","score":0.470624715089798},{"id":"https://openalex.org/keywords/word","display_name":"Word (group theory)","score":0.4465585947036743},{"id":"https://openalex.org/keywords/tree-structure","display_name":"Tree structure","score":0.4387710988521576},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.39682736992836},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.2930327355861664},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.26360607147216797},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2165098786354065},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.12090909481048584},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.06607255339622498},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.06170874834060669}],"concepts":[{"id":"https://openalex.org/C155745195","wikidata":"https://www.wikidata.org/wiki/Q1164179","display_name":"Comparator","level":3,"score":0.947304368019104},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8015297055244446},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6864755749702454},{"id":"https://openalex.org/C197855036","wikidata":"https://www.wikidata.org/wiki/Q380172","display_name":"Binary tree","level":2,"score":0.6446885466575623},{"id":"https://openalex.org/C48372109","wikidata":"https://www.wikidata.org/wiki/Q3913","display_name":"Binary number","level":2,"score":0.6086040735244751},{"id":"https://openalex.org/C113174947","wikidata":"https://www.wikidata.org/wiki/Q2859736","display_name":"Tree (set theory)","level":2,"score":0.470624715089798},{"id":"https://openalex.org/C90805587","wikidata":"https://www.wikidata.org/wiki/Q10944557","display_name":"Word (group theory)","level":2,"score":0.4465585947036743},{"id":"https://openalex.org/C163797641","wikidata":"https://www.wikidata.org/wiki/Q2067937","display_name":"Tree structure","level":3,"score":0.4387710988521576},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.39682736992836},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.2930327355861664},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.26360607147216797},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2165098786354065},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.12090909481048584},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.06607255339622498},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.06170874834060669},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1007/978-3-319-24369-6_32","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-319-24369-6_32","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},{"id":"pmh:oai:HAL:hal-01444482v1","is_oa":true,"landing_page_url":"https://inria.hal.science/hal-01444482","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"14th Computer Information Systems and Industrial Management (CISIM), Sep 2015, Warsaw, Poland. pp.386-396, &#x27E8;10.1007/978-3-319-24369-6_32&#x27E9;","raw_type":"Conference papers"}],"best_oa_location":{"id":"pmh:oai:HAL:hal-01444482v1","is_oa":true,"landing_page_url":"https://inria.hal.science/hal-01444482","pdf_url":null,"source":null,"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"14th Computer Information Systems and Industrial Management (CISIM), Sep 2015, Warsaw, Poland. pp.386-396, &#x27E8;10.1007/978-3-319-24369-6_32&#x27E9;","raw_type":"Conference papers"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1972913619","https://openalex.org/W1973974066","https://openalex.org/W1979588383","https://openalex.org/W1992288365","https://openalex.org/W2002526514","https://openalex.org/W2009513241","https://openalex.org/W2027104619","https://openalex.org/W2061528230","https://openalex.org/W2099844776","https://openalex.org/W2128602413","https://openalex.org/W2151829358","https://openalex.org/W2171123968","https://openalex.org/W2540548506","https://openalex.org/W2545738139"],"related_works":["https://openalex.org/W2034349229","https://openalex.org/W1972415042","https://openalex.org/W4366783034","https://openalex.org/W2005410346","https://openalex.org/W2890975198","https://openalex.org/W1978807050","https://openalex.org/W2067642082","https://openalex.org/W1945695511","https://openalex.org/W1979994068","https://openalex.org/W1597345325"],"abstract_inverted_index":{"The":[0,23,39],"article":[1],"considers":[2],"the":[3,29,65,70],"general":[4],"synthesis":[5],"technique":[6],"of":[7,17,69,78],"hierarchical":[8,25],"tree":[9],"structures":[10],"on":[11],"FPGA/SoC":[12,31],"for":[13,28,51],"binary":[14],"comparators.":[15],"Designing":[16],"first":[18],"level":[19],"comparators":[20,54],"is":[21,33],"given.":[22],"best":[24],"comparator":[26],"structure":[27],"specific":[30],"family":[32],"found":[34],"empirically":[35],"by":[36,61],"experimental":[37],"researches.":[38],"offered":[40,71],"method":[41,72],"allows":[42],"reducing":[43],"an":[44,56],"area":[45],"from":[46],"5.3%":[47],"to":[48],"43.0%,":[49],"and":[50,75],"high":[52],"bitwidth":[53],"(with":[55],"input":[57],"word":[58],"length":[59],"1024)":[60],"2.225":[62],"times.":[63],"In":[64],"conclusion":[66],"additional":[67],"opportunities":[68],"are":[73,81],"marked,":[74],"main":[76],"directions":[77],"further":[79],"researches":[80],"presented.":[82]},"counts_by_year":[],"updated_date":"2026-03-10T16:38:18.471706","created_date":"2025-10-10T00:00:00"}
