{"id":"https://openalex.org/W2412401244","doi":"https://doi.org/10.1007/978-3-319-08422-0_68","title":"Implementation of an Efficient Library for Asynchronous Circuit Design with Synopsys","display_name":"Implementation of an Efficient Library for Asynchronous Circuit Design with Synopsys","publication_year":2014,"publication_date":"2014-08-12","ids":{"openalex":"https://openalex.org/W2412401244","doi":"https://doi.org/10.1007/978-3-319-08422-0_68","mag":"2412401244"},"language":"en","primary_location":{"id":"doi:10.1007/978-3-319-08422-0_68","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-319-08422-0_68","pdf_url":null,"source":{"id":"https://openalex.org/S2764905038","display_name":"Advances in intelligent systems and computing","issn_l":"2194-5357","issn":["2194-5357","2194-5365"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319965","host_organization_name":"Springer Nature","host_organization_lineage":["https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Advances in Intelligent Systems and Computing","raw_type":"book-chapter"},"type":"book-chapter","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5008651431","display_name":"Tri Caohuu","orcid":null},"institutions":[{"id":"https://openalex.org/I51504820","display_name":"San Jose State University","ror":"https://ror.org/04qyvz380","country_code":"US","type":"education","lineage":["https://openalex.org/I51504820"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tri Caohuu","raw_affiliation_strings":["Department of Electrical Engineering, San Jos\u00e9 State University, San Jos\u00e9, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, San Jos\u00e9 State University, San Jos\u00e9, CA, USA","institution_ids":["https://openalex.org/I51504820"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5041062800","display_name":"J. Gordon Edwards","orcid":null},"institutions":[{"id":"https://openalex.org/I51504820","display_name":"San Jose State University","ror":"https://ror.org/04qyvz380","country_code":"US","type":"education","lineage":["https://openalex.org/I51504820"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"John Edwards","raw_affiliation_strings":["Department of Electrical Engineering, San Jos\u00e9 State University, San Jos\u00e9, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, San Jos\u00e9 State University, San Jos\u00e9, CA, USA","institution_ids":["https://openalex.org/I51504820"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I51504820"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.18402025,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"465","last_page":"471"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9937999844551086,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9830999970436096,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.8774823546409607},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7744901180267334},{"id":"https://openalex.org/keywords/fifo","display_name":"FIFO (computing and electronics)","score":0.737922191619873},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6782740950584412},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.5270566940307617},{"id":"https://openalex.org/keywords/asynchronous-system","display_name":"Asynchronous system","score":0.5062772035598755},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.5035185217857361},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4846256673336029},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.4724184572696686},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2705315947532654},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.1850324273109436},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.15197286009788513},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.10500088334083557},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09235954284667969}],"concepts":[{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.8774823546409607},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7744901180267334},{"id":"https://openalex.org/C2777145635","wikidata":"https://www.wikidata.org/wiki/Q515636","display_name":"FIFO (computing and electronics)","level":2,"score":0.737922191619873},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6782740950584412},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.5270566940307617},{"id":"https://openalex.org/C7923308","wikidata":"https://www.wikidata.org/wiki/Q4812211","display_name":"Asynchronous system","level":5,"score":0.5062772035598755},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.5035185217857361},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4846256673336029},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.4724184572696686},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2705315947532654},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.1850324273109436},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.15197286009788513},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.10500088334083557},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09235954284667969},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/978-3-319-08422-0_68","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-319-08422-0_68","pdf_url":null,"source":{"id":"https://openalex.org/S2764905038","display_name":"Advances in intelligent systems and computing","issn_l":"2194-5357","issn":["2194-5357","2194-5365"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319965","host_organization_name":"Springer Nature","host_organization_lineage":["https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Advances in Intelligent Systems and Computing","raw_type":"book-chapter"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W2116710570","https://openalex.org/W2153317824","https://openalex.org/W2161622842","https://openalex.org/W2169222350","https://openalex.org/W2806490410","https://openalex.org/W6684763225"],"related_works":["https://openalex.org/W4312516786","https://openalex.org/W2109350679","https://openalex.org/W3094139610","https://openalex.org/W1647623034","https://openalex.org/W2367585599","https://openalex.org/W1984298705","https://openalex.org/W2364442604","https://openalex.org/W2162490878","https://openalex.org/W2412401244","https://openalex.org/W2034785246"],"abstract_inverted_index":null,"counts_by_year":[{"year":2020,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
