{"id":"https://openalex.org/W2341512806","doi":"https://doi.org/10.1007/978-3-319-04370-8_13","title":"A Reconfigurable Functional Unit for Modular Operations","display_name":"A Reconfigurable Functional Unit for Modular Operations","publication_year":2014,"publication_date":"2014-01-01","ids":{"openalex":"https://openalex.org/W2341512806","doi":"https://doi.org/10.1007/978-3-319-04370-8_13","mag":"2341512806"},"language":"en","primary_location":{"id":"doi:10.1007/978-3-319-04370-8_13","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-319-04370-8_13","pdf_url":null,"source":{"id":"https://openalex.org/S4210179954","display_name":"Lecture notes in electrical engineering","issn_l":"1876-1100","issn":["1876-1100","1876-1119"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Electrical Engineering","raw_type":"book-chapter"},"type":"book-chapter","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5028297120","display_name":"G.C. Cardarilli","orcid":"https://orcid.org/0000-0002-7444-876X"},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Gian Carlo Cardarilli","raw_affiliation_strings":["University of Rome \u201cTor Vergata\u201d, Via del Politecnico 1, 00191, Rome, Italy","University of Rome \"Tor Vergata\", Via del Politecnico 1, 00191, Rome, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Rome \u201cTor Vergata\u201d, Via del Politecnico 1, 00191, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]},{"raw_affiliation_string":"University of Rome \"Tor Vergata\", Via del Politecnico 1, 00191, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063300969","display_name":"Luca Di Nunzio","orcid":"https://orcid.org/0000-0002-4312-7939"},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Luca Di Nunzio","raw_affiliation_strings":["University of Rome \u201cTor Vergata\u201d, Via del Politecnico 1, 00191, Rome, Italy","University of Rome \"Tor Vergata\", Via del Politecnico 1, 00191, Rome, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Rome \u201cTor Vergata\u201d, Via del Politecnico 1, 00191, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]},{"raw_affiliation_string":"University of Rome \"Tor Vergata\", Via del Politecnico 1, 00191, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048482308","display_name":"Rocco Fazzolari","orcid":"https://orcid.org/0000-0002-7383-2663"},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Rocco Fazzolari","raw_affiliation_strings":["University of Rome \u201cTor Vergata\u201d, Via del Politecnico 1, 00191, Rome, Italy","University of Rome \"Tor Vergata\", Via del Politecnico 1, 00191, Rome, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Rome \u201cTor Vergata\u201d, Via del Politecnico 1, 00191, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]},{"raw_affiliation_string":"University of Rome \"Tor Vergata\", Via del Politecnico 1, 00191, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010562631","display_name":"Salvatore Pontarelli","orcid":"https://orcid.org/0000-0002-3626-6404"},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Salvatore Pontarelli","raw_affiliation_strings":["University of Rome \u201cTor Vergata\u201d, Via del Politecnico 1, 00191, Rome, Italy","University of Rome \"Tor Vergata\", Via del Politecnico 1, 00191, Rome, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Rome \u201cTor Vergata\u201d, Via del Politecnico 1, 00191, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]},{"raw_affiliation_string":"University of Rome \"Tor Vergata\", Via del Politecnico 1, 00191, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5000963583","display_name":"M. Re","orcid":"https://orcid.org/0000-0001-9046-1318"},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Marco Re","raw_affiliation_strings":["University of Rome \u201cTor Vergata\u201d, Via del Politecnico 1, 00191, Rome, Italy","University of Rome \"Tor Vergata\", Via del Politecnico 1, 00191, Rome, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Rome \u201cTor Vergata\u201d, Via del Politecnico 1, 00191, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]},{"raw_affiliation_string":"University of Rome \"Tor Vergata\", Via del Politecnico 1, 00191, Rome, Italy","institution_ids":["https://openalex.org/I116067653"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5000963583","https://openalex.org/A5010562631","https://openalex.org/A5028297120","https://openalex.org/A5048482308","https://openalex.org/A5063300969"],"corresponding_institution_ids":["https://openalex.org/I116067653"],"apc_list":null,"apc_paid":null,"fwci":2.1546,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.88479263,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"141","last_page":"152"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11693","display_name":"Cryptography and Residue Arithmetic","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11693","display_name":"Cryptography and Residue Arithmetic","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1710","display_name":"Information Systems"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.8319907188415527},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.7794456481933594},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7508342266082764},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.513794481754303},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.48002758622169495},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.46131420135498047},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.42851901054382324},{"id":"https://openalex.org/keywords/modular-arithmetic","display_name":"Modular arithmetic","score":0.426555335521698},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.41758131980895996},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.1452837884426117},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.0737176239490509}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.8319907188415527},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.7794456481933594},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7508342266082764},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.513794481754303},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.48002758622169495},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.46131420135498047},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.42851901054382324},{"id":"https://openalex.org/C32049820","wikidata":"https://www.wikidata.org/wiki/Q319400","display_name":"Modular arithmetic","level":3,"score":0.426555335521698},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.41758131980895996},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.1452837884426117},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0737176239490509},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1007/978-3-319-04370-8_13","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-319-04370-8_13","pdf_url":null,"source":{"id":"https://openalex.org/S4210179954","display_name":"Lecture notes in electrical engineering","issn_l":"1876-1100","issn":["1876-1100","1876-1119"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Electrical Engineering","raw_type":"book-chapter"},{"id":"pmh:oai:art.torvergata.it:2108/105949","is_oa":false,"landing_page_url":"http://link.springer.com/chapter/10.1007/978-3-319-04370-8_13","pdf_url":null,"source":{"id":"https://openalex.org/S4306400993","display_name":"Cineca Institutional Research Information System (Tor Vergata University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I116067653","host_organization_name":"University of Rome Tor Vergata","host_organization_lineage":["https://openalex.org/I116067653"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/bookPart"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.7099999785423279,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W572742053","https://openalex.org/W1747765598","https://openalex.org/W1882870471","https://openalex.org/W1981998307","https://openalex.org/W2004814164","https://openalex.org/W2025285350","https://openalex.org/W2117919933","https://openalex.org/W2128812806","https://openalex.org/W2141586470","https://openalex.org/W2148911285","https://openalex.org/W2149307572","https://openalex.org/W2159126185","https://openalex.org/W2752853835","https://openalex.org/W4234345682","https://openalex.org/W4289126832"],"related_works":["https://openalex.org/W2058965144","https://openalex.org/W2164382479","https://openalex.org/W98480971","https://openalex.org/W2150291671","https://openalex.org/W2027972911","https://openalex.org/W2146343568","https://openalex.org/W2013643406","https://openalex.org/W2157978810","https://openalex.org/W2255754718","https://openalex.org/W2353466882"],"abstract_inverted_index":null,"counts_by_year":[{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2026-08-04T08:18:43.703281","created_date":"2025-10-10T00:00:00"}
