{"id":"https://openalex.org/W4390790381","doi":"https://doi.org/10.1007/978-3-031-48121-5_5","title":"A Universal Hardware Emulator for Verification IPs on FPGA: A Novel and Low-Cost Approach","display_name":"A Universal Hardware Emulator for Verification IPs on FPGA: A Novel and Low-Cost Approach","publication_year":2024,"publication_date":"2024-01-01","ids":{"openalex":"https://openalex.org/W4390790381","doi":"https://doi.org/10.1007/978-3-031-48121-5_5"},"language":"en","primary_location":{"id":"doi:10.1007/978-3-031-48121-5_5","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-031-48121-5_5","pdf_url":null,"source":{"id":"https://openalex.org/S4210179954","display_name":"Lecture notes in electrical engineering","issn_l":"1876-1100","issn":["1876-1100","1876-1119"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Electrical Engineering","raw_type":"book-chapter"},"type":"book-chapter","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5059337172","display_name":"Saeid Jamili","orcid":"https://orcid.org/0009-0003-8624-4048"},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Saeid Jamili","raw_affiliation_strings":["Sapienza Universit\u00e1 di Roma, Via Eudossiana, 18, 00184, Roma, RM, Italy"],"affiliations":[{"raw_affiliation_string":"Sapienza Universit\u00e1 di Roma, Via Eudossiana, 18, 00184, Roma, RM, Italy","institution_ids":["https://openalex.org/I861853513"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044942957","display_name":"Antonio Mastrandrea","orcid":"https://orcid.org/0000-0003-4243-1258"},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Antonio Mastrandrea","raw_affiliation_strings":["Sapienza Universit\u00e1 di Roma, Via Eudossiana, 18, 00184, Roma, RM, Italy"],"affiliations":[{"raw_affiliation_string":"Sapienza Universit\u00e1 di Roma, Via Eudossiana, 18, 00184, Roma, RM, Italy","institution_ids":["https://openalex.org/I861853513"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060706503","display_name":"Abdallah Cheikh","orcid":"https://orcid.org/0000-0003-4495-5960"},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Abdallah Cheikh","raw_affiliation_strings":["Sapienza Universit\u00e1 di Roma, Via Eudossiana, 18, 00184, Roma, RM, Italy"],"affiliations":[{"raw_affiliation_string":"Sapienza Universit\u00e1 di Roma, Via Eudossiana, 18, 00184, Roma, RM, Italy","institution_ids":["https://openalex.org/I861853513"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002051086","display_name":"Marcello Barbirotta","orcid":"https://orcid.org/0000-0002-1902-7188"},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Marcello Barbirotta","raw_affiliation_strings":["Sapienza Universit\u00e1 di Roma, Via Eudossiana, 18, 00184, Roma, RM, Italy"],"affiliations":[{"raw_affiliation_string":"Sapienza Universit\u00e1 di Roma, Via Eudossiana, 18, 00184, Roma, RM, Italy","institution_ids":["https://openalex.org/I861853513"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045257843","display_name":"Francesco Menichelli","orcid":null},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Francesco Menichelli","raw_affiliation_strings":["Sapienza Universit\u00e1 di Roma, Via Eudossiana, 18, 00184, Roma, RM, Italy"],"affiliations":[{"raw_affiliation_string":"Sapienza Universit\u00e1 di Roma, Via Eudossiana, 18, 00184, Roma, RM, Italy","institution_ids":["https://openalex.org/I861853513"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059848419","display_name":"Marco Angioli","orcid":"https://orcid.org/0009-0002-5955-8378"},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Marco Angioli","raw_affiliation_strings":["Sapienza Universit\u00e1 di Roma, Via Eudossiana, 18, 00184, Roma, RM, Italy"],"affiliations":[{"raw_affiliation_string":"Sapienza Universit\u00e1 di Roma, Via Eudossiana, 18, 00184, Roma, RM, Italy","institution_ids":["https://openalex.org/I861853513"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5067054447","display_name":"Mauro Olivieri","orcid":"https://orcid.org/0000-0002-0214-9904"},"institutions":[{"id":"https://openalex.org/I861853513","display_name":"Sapienza University of Rome","ror":"https://ror.org/02be6w209","country_code":"IT","type":"education","lineage":["https://openalex.org/I861853513"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Mauro Olivieri","raw_affiliation_strings":["Sapienza Universit\u00e1 di Roma, Via Eudossiana, 18, 00184, Roma, RM, Italy"],"affiliations":[{"raw_affiliation_string":"Sapienza Universit\u00e1 di Roma, Via Eudossiana, 18, 00184, Roma, RM, Italy","institution_ids":["https://openalex.org/I861853513"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5059337172"],"corresponding_institution_ids":["https://openalex.org/I861853513"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.01435596,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"36","last_page":"41"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7588036060333252},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.650068998336792},{"id":"https://openalex.org/keywords/intelligent-verification","display_name":"Intelligent verification","score":0.5709009766578674},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5624175667762756},{"id":"https://openalex.org/keywords/functional-verification","display_name":"Functional verification","score":0.5599645972251892},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4729720652103424},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4566745460033417},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.4396825134754181},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4380171597003937},{"id":"https://openalex.org/keywords/high-level-verification","display_name":"High-level verification","score":0.4204336702823639},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.25302863121032715},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.1969008445739746},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1686582863330841},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.1188039481639862}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7588036060333252},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.650068998336792},{"id":"https://openalex.org/C3406870","wikidata":"https://www.wikidata.org/wiki/Q6044160","display_name":"Intelligent verification","level":5,"score":0.5709009766578674},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5624175667762756},{"id":"https://openalex.org/C62460635","wikidata":"https://www.wikidata.org/wiki/Q5508853","display_name":"Functional verification","level":3,"score":0.5599645972251892},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4729720652103424},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4566745460033417},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.4396825134754181},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4380171597003937},{"id":"https://openalex.org/C187250869","wikidata":"https://www.wikidata.org/wiki/Q5754573","display_name":"High-level verification","level":5,"score":0.4204336702823639},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.25302863121032715},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.1969008445739746},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1686582863330841},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.1188039481639862},{"id":"https://openalex.org/C149091818","wikidata":"https://www.wikidata.org/wiki/Q2429814","display_name":"Software system","level":3,"score":0.0},{"id":"https://openalex.org/C186846655","wikidata":"https://www.wikidata.org/wiki/Q3398377","display_name":"Software construction","level":4,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1007/978-3-031-48121-5_5","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-031-48121-5_5","pdf_url":null,"source":{"id":"https://openalex.org/S4210179954","display_name":"Lecture notes in electrical engineering","issn_l":"1876-1100","issn":["1876-1100","1876-1119"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Electrical Engineering","raw_type":"book-chapter"},{"id":"pmh:oai:iris.uniroma1.it:11573/1722601","is_oa":false,"landing_page_url":"https://hdl.handle.net/11573/1722601","pdf_url":null,"source":{"id":"https://openalex.org/S4377196107","display_name":"IRIS Research product catalog (Sapienza University of Rome)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.6200000047683716,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W2033105749","https://openalex.org/W2084373512","https://openalex.org/W2725129414","https://openalex.org/W2946072469","https://openalex.org/W4311995762","https://openalex.org/W4319870528","https://openalex.org/W4367336445"],"related_works":["https://openalex.org/W2361881307","https://openalex.org/W2392047570","https://openalex.org/W4205300843","https://openalex.org/W2929969821","https://openalex.org/W3155012083","https://openalex.org/W2354470518","https://openalex.org/W3120172095","https://openalex.org/W4379116333","https://openalex.org/W2357142578","https://openalex.org/W1550280164"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2026-01-23T23:20:30.427331","created_date":"2025-10-10T00:00:00"}
