{"id":"https://openalex.org/W4292632186","doi":"https://doi.org/10.1007/978-3-030-98347-5_7","title":"Approximate Logic Synthesis for FPGA by Decomposition","display_name":"Approximate Logic Synthesis for FPGA by Decomposition","publication_year":2012,"publication_date":"2012-02-24","ids":{"openalex":"https://openalex.org/W4292632186","doi":"https://doi.org/10.1007/978-3-030-98347-5_7"},"language":"en","primary_location":{"id":"doi:10.1007/978-3-030-98347-5_7","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-030-98347-5_7","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Approximate Computing","raw_type":"book-chapter"},"type":"book-chapter","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5047128664","display_name":"Zhiyuan Xiang","orcid":null},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhiyuan Xiang","raw_affiliation_strings":["University of Michigan-Shanghai Jiao Tong University Joint Institute, Shanghai Jiao Tong University, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Michigan-Shanghai Jiao Tong University Joint Institute, Shanghai Jiao Tong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007065845","display_name":"Niyiqiu Liu","orcid":null},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Niyiqiu Liu","raw_affiliation_strings":["University of Michigan-Shanghai Jiao Tong University Joint Institute, Shanghai Jiao Tong University, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Michigan-Shanghai Jiao Tong University Joint Institute, Shanghai Jiao Tong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5003684287","display_name":"Yue Yao","orcid":"https://orcid.org/0000-0001-8523-5156"},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yue Yao","raw_affiliation_strings":["School of Computer Science, Carnegie Mellon University, Pittsburgh, PA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Computer Science, Carnegie Mellon University, Pittsburgh, PA, USA","institution_ids":["https://openalex.org/I74973139"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045464812","display_name":"Fan Yang","orcid":"https://orcid.org/0000-0003-2164-8175"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]},{"id":"https://openalex.org/I4210132426","display_name":"Shanghai Fudan Microelectronics (China)","ror":"https://ror.org/02vfj3j86","country_code":"CN","type":"company","lineage":["https://openalex.org/I4210132426"]},{"id":"https://openalex.org/I4391767673","display_name":"State Key Laboratory of ASIC and System","ror":"https://ror.org/01mamgv83","country_code":null,"type":"facility","lineage":["https://openalex.org/I24943067","https://openalex.org/I4391767673"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Fan Yang","raw_affiliation_strings":["State Key Laboratory of ASIC & System; Microelectronics Department, Fudan University, Shanghai, China","Microelectronics Department, Fudan University, Shanghai, China","State Key Laboratory of ASIC & System"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC & System; Microelectronics Department, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I4210132426"]},{"raw_affiliation_string":"Microelectronics Department, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I4210132426","https://openalex.org/I24943067"]},{"raw_affiliation_string":"State Key Laboratory of ASIC & System","institution_ids":["https://openalex.org/I4391767673"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5054211420","display_name":"Cheng Zhuo","orcid":"https://orcid.org/0000-0002-2610-7522"},"institutions":[{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Cheng Zhuo","raw_affiliation_strings":["College of Information Science and Electronic Engineering, Zhejiang University, Hangzhou, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"College of Information Science and Electronic Engineering, Zhejiang University, Hangzhou, China","institution_ids":["https://openalex.org/I76130692"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5036572182","display_name":"Weikang Qian","orcid":"https://orcid.org/0000-0002-5129-9431"},"institutions":[{"id":"https://openalex.org/I183067930","display_name":"Shanghai Jiao Tong University","ror":"https://ror.org/0220qvk04","country_code":"CN","type":"education","lineage":["https://openalex.org/I183067930"]},{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Weikang Qian","raw_affiliation_strings":["State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","University of Michigan-Shanghai Jiao Tong University Joint Institute and MoE Key Laboratory of Artificial Intelligence, Shanghai Jiao Tong University, Shanghai, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Laboratory of ASIC & System, Fudan University, Shanghai, China","institution_ids":["https://openalex.org/I24943067"]},{"raw_affiliation_string":"University of Michigan-Shanghai Jiao Tong University Joint Institute and MoE Key Laboratory of Artificial Intelligence, Shanghai Jiao Tong University, Shanghai, China","institution_ids":["https://openalex.org/I183067930"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5036572182"],"corresponding_institution_ids":["https://openalex.org/I183067930","https://openalex.org/I24943067"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.5449473,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"149","last_page":"174"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.9061670303344727},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8206571936607361},{"id":"https://openalex.org/keywords/disjoint-sets","display_name":"Disjoint sets","score":0.7727195024490356},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6570512056350708},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5377851128578186},{"id":"https://openalex.org/keywords/decomposition","display_name":"Decomposition","score":0.49431419372558594},{"id":"https://openalex.org/keywords/table","display_name":"Table (database)","score":0.47045814990997314},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4449710249900818},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.42827823758125305},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.4067229926586151},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3970237076282501},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2507072687149048},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.24080824851989746},{"id":"https://openalex.org/keywords/discrete-mathematics","display_name":"Discrete mathematics","score":0.10786661505699158}],"concepts":[{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.9061670303344727},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8206571936607361},{"id":"https://openalex.org/C45340560","wikidata":"https://www.wikidata.org/wiki/Q215382","display_name":"Disjoint sets","level":2,"score":0.7727195024490356},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6570512056350708},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5377851128578186},{"id":"https://openalex.org/C124681953","wikidata":"https://www.wikidata.org/wiki/Q339062","display_name":"Decomposition","level":2,"score":0.49431419372558594},{"id":"https://openalex.org/C45235069","wikidata":"https://www.wikidata.org/wiki/Q278425","display_name":"Table (database)","level":2,"score":0.47045814990997314},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4449710249900818},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.42827823758125305},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.4067229926586151},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3970237076282501},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2507072687149048},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.24080824851989746},{"id":"https://openalex.org/C118615104","wikidata":"https://www.wikidata.org/wiki/Q121416","display_name":"Discrete mathematics","level":1,"score":0.10786661505699158},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C18903297","wikidata":"https://www.wikidata.org/wiki/Q7150","display_name":"Ecology","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C124101348","wikidata":"https://www.wikidata.org/wiki/Q172491","display_name":"Data mining","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/978-3-030-98347-5_7","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-030-98347-5_7","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Approximate Computing","raw_type":"book-chapter"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1996431812","https://openalex.org/W2034581485","https://openalex.org/W2052067881","https://openalex.org/W2105715355","https://openalex.org/W2153848924","https://openalex.org/W2254450385","https://openalex.org/W2265166184","https://openalex.org/W2323419649","https://openalex.org/W2537354715","https://openalex.org/W2588565458","https://openalex.org/W2769903157","https://openalex.org/W2798497431","https://openalex.org/W2804278059","https://openalex.org/W2944333218","https://openalex.org/W3092498068","https://openalex.org/W4200573127","https://openalex.org/W4234143475","https://openalex.org/W4235991875","https://openalex.org/W4240315454","https://openalex.org/W4245558464"],"related_works":["https://openalex.org/W2125609625","https://openalex.org/W2005870728","https://openalex.org/W1570722643","https://openalex.org/W2149339590","https://openalex.org/W2155289750","https://openalex.org/W2189515211","https://openalex.org/W2547549925","https://openalex.org/W2019455687","https://openalex.org/W1533253004","https://openalex.org/W2394360355"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2026-05-22T09:01:20.584952","created_date":"2025-10-10T00:00:00"}
