{"id":"https://openalex.org/W3182711606","doi":"https://doi.org/10.1007/978-3-030-81641-4_13","title":"3D Nanofabric: Layout Challenges and Solutions for Ultra-scaled Logic Designs","display_name":"3D Nanofabric: Layout Challenges and Solutions for Ultra-scaled Logic Designs","publication_year":2021,"publication_date":"2021-01-01","ids":{"openalex":"https://openalex.org/W3182711606","doi":"https://doi.org/10.1007/978-3-030-81641-4_13","mag":"3182711606"},"language":"en","primary_location":{"id":"doi:10.1007/978-3-030-81641-4_13","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-030-81641-4_13","pdf_url":null,"source":{"id":"https://openalex.org/S4210185096","display_name":"IFIP advances in information and communication technology","issn_l":"1868-422X","issn":["1868-422X","1868-4238"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IFIP Advances in Information and Communication Technology","raw_type":"book-chapter"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://inria.hal.science/hal-03759735","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5055536889","display_name":"Edouard Giacomin","orcid":"https://orcid.org/0000-0002-5415-1870"},"institutions":[{"id":"https://openalex.org/I223532165","display_name":"University of Utah","ror":"https://ror.org/03r0ha626","country_code":"US","type":"education","lineage":["https://openalex.org/I223532165"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Edouard Giacomin","raw_affiliation_strings":["University of Utah, Salt Lake City, UT, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Utah, Salt Lake City, UT, USA","institution_ids":["https://openalex.org/I223532165"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071436641","display_name":"Juergen Boemmels","orcid":"https://orcid.org/0000-0002-8761-5213"},"institutions":[{"id":"https://openalex.org/I4210114974","display_name":"IMEC","ror":"https://ror.org/02kcbn207","country_code":"BE","type":"nonprofit","lineage":["https://openalex.org/I4210114974"]}],"countries":["BE"],"is_corresponding":false,"raw_author_name":"Juergen Boemmels","raw_affiliation_strings":["IMEC, Leuven, Belgium"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IMEC, Leuven, Belgium","institution_ids":["https://openalex.org/I4210114974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103112055","display_name":"Julien Ryckaert","orcid":"https://orcid.org/0009-0001-0140-3042"},"institutions":[{"id":"https://openalex.org/I4210114974","display_name":"IMEC","ror":"https://ror.org/02kcbn207","country_code":"BE","type":"nonprofit","lineage":["https://openalex.org/I4210114974"]}],"countries":["BE"],"is_corresponding":false,"raw_author_name":"Julien Ryckaert","raw_affiliation_strings":["IMEC, Leuven, Belgium"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IMEC, Leuven, Belgium","institution_ids":["https://openalex.org/I4210114974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5033235745","display_name":"Francky Catthoor","orcid":"https://orcid.org/0000-0002-3599-8515"},"institutions":[{"id":"https://openalex.org/I4210114974","display_name":"IMEC","ror":"https://ror.org/02kcbn207","country_code":"BE","type":"nonprofit","lineage":["https://openalex.org/I4210114974"]},{"id":"https://openalex.org/I99464096","display_name":"KU Leuven","ror":"https://ror.org/05f950310","country_code":"BE","type":"education","lineage":["https://openalex.org/I99464096"]}],"countries":["BE"],"is_corresponding":false,"raw_author_name":"Francky Catthoor","raw_affiliation_strings":["IMEC, Leuven, Belgium","KU Leuven, Leuven, Belgium"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IMEC, Leuven, Belgium","institution_ids":["https://openalex.org/I4210114974"]},{"raw_affiliation_string":"KU Leuven, Leuven, Belgium","institution_ids":["https://openalex.org/I99464096"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5002568331","display_name":"Pierre\u2010Emmanuel Gaillardon","orcid":"https://orcid.org/0000-0003-3634-3999"},"institutions":[{"id":"https://openalex.org/I223532165","display_name":"University of Utah","ror":"https://ror.org/03r0ha626","country_code":"US","type":"education","lineage":["https://openalex.org/I223532165"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Pierre-Emmanuel Gaillardon","raw_affiliation_strings":["University of Utah, Salt Lake City, UT, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Utah, Salt Lake City, UT, USA","institution_ids":["https://openalex.org/I223532165"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"279","last_page":"300"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.8013267517089844},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6564498543739319},{"id":"https://openalex.org/keywords/footprint","display_name":"Footprint","score":0.5889958143234253},{"id":"https://openalex.org/keywords/three-dimensional-integrated-circuit","display_name":"Three-dimensional integrated circuit","score":0.5762383341789246},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.5293664932250977},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5166738033294678},{"id":"https://openalex.org/keywords/domino-logic","display_name":"Domino logic","score":0.4943702220916748},{"id":"https://openalex.org/keywords/planar","display_name":"Planar","score":0.4923337697982788},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.46181073784828186},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.4603421986103058},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.45545831322669983},{"id":"https://openalex.org/keywords/stacking","display_name":"Stacking","score":0.43780145049095154},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.42950600385665894},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.42526233196258545},{"id":"https://openalex.org/keywords/place-and-route","display_name":"Place and route","score":0.41172677278518677},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3586476147174835},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3536655902862549},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.35105857253074646},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.3114737272262573},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2864670157432556},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.1981770098209381},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1191604733467102}],"concepts":[{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.8013267517089844},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6564498543739319},{"id":"https://openalex.org/C132943942","wikidata":"https://www.wikidata.org/wiki/Q2562511","display_name":"Footprint","level":2,"score":0.5889958143234253},{"id":"https://openalex.org/C59088047","wikidata":"https://www.wikidata.org/wiki/Q229370","display_name":"Three-dimensional integrated circuit","level":3,"score":0.5762383341789246},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.5293664932250977},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5166738033294678},{"id":"https://openalex.org/C2777555262","wikidata":"https://www.wikidata.org/wiki/Q173391","display_name":"Domino logic","level":5,"score":0.4943702220916748},{"id":"https://openalex.org/C134786449","wikidata":"https://www.wikidata.org/wiki/Q3391255","display_name":"Planar","level":2,"score":0.4923337697982788},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.46181073784828186},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.4603421986103058},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.45545831322669983},{"id":"https://openalex.org/C33347731","wikidata":"https://www.wikidata.org/wiki/Q285210","display_name":"Stacking","level":2,"score":0.43780145049095154},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.42950600385665894},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.42526233196258545},{"id":"https://openalex.org/C127879752","wikidata":"https://www.wikidata.org/wiki/Q3390760","display_name":"Place and route","level":3,"score":0.41172677278518677},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3586476147174835},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3536655902862549},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.35105857253074646},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.3114737272262573},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2864670157432556},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.1981770098209381},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1191604733467102},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C121684516","wikidata":"https://www.wikidata.org/wiki/Q7600677","display_name":"Computer graphics (images)","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C46141821","wikidata":"https://www.wikidata.org/wiki/Q209402","display_name":"Nuclear magnetic resonance","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1007/978-3-030-81641-4_13","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-030-81641-4_13","pdf_url":null,"source":{"id":"https://openalex.org/S4210185096","display_name":"IFIP advances in information and communication technology","issn_l":"1868-422X","issn":["1868-422X","1868-4238"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IFIP Advances in Information and Communication Technology","raw_type":"book-chapter"},{"id":"pmh:oai:HAL:hal-03759735v1","is_oa":true,"landing_page_url":"https://inria.hal.science/hal-03759735","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"28th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC), Oct 2020, Salt Lake City, UT, United States. pp.279-300, ⟨10.1007/978-3-030-81641-4_13⟩","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":{"id":"pmh:oai:HAL:hal-03759735v1","is_oa":true,"landing_page_url":"https://inria.hal.science/hal-03759735","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"28th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC), Oct 2020, Salt Lake City, UT, United States. pp.279-300, ⟨10.1007/978-3-030-81641-4_13⟩","raw_type":"info:eu-repo/semantics/conferenceObject"},"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.4699999988079071,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":27,"referenced_works":["https://openalex.org/W1587386427","https://openalex.org/W1966797259","https://openalex.org/W1972367194","https://openalex.org/W2004305691","https://openalex.org/W2034975188","https://openalex.org/W2145601433","https://openalex.org/W2146704626","https://openalex.org/W2147560018","https://openalex.org/W2150190846","https://openalex.org/W2154133941","https://openalex.org/W2154368093","https://openalex.org/W2209394967","https://openalex.org/W2346205343","https://openalex.org/W2461620692","https://openalex.org/W2520174958","https://openalex.org/W2525903134","https://openalex.org/W2578406675","https://openalex.org/W2731422849","https://openalex.org/W2787438330","https://openalex.org/W2810999708","https://openalex.org/W2899234473","https://openalex.org/W2913596336","https://openalex.org/W2920916186","https://openalex.org/W2921558526","https://openalex.org/W2922344031","https://openalex.org/W2962848119","https://openalex.org/W3131522514"],"related_works":["https://openalex.org/W2142909193","https://openalex.org/W2123076670","https://openalex.org/W2157878629","https://openalex.org/W2326620043","https://openalex.org/W2024133544","https://openalex.org/W1995821058","https://openalex.org/W2126475478","https://openalex.org/W2526357853","https://openalex.org/W146048418","https://openalex.org/W2543290882"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2026-07-15T18:14:33.161393","created_date":"2025-10-10T00:00:00"}