{"id":"https://openalex.org/W4211193615","doi":"https://doi.org/10.1007/978-3-030-78841-4_4","title":"Hardware IP Protection Using Register Transfer Level Locking and Obfuscation of Control and Data Flow","display_name":"Hardware IP Protection Using Register Transfer Level Locking and Obfuscation of Control and Data Flow","publication_year":2021,"publication_date":"2021-05-28","ids":{"openalex":"https://openalex.org/W4211193615","doi":"https://doi.org/10.1007/978-3-030-78841-4_4"},"language":"en","primary_location":{"id":"doi:10.1007/978-3-030-78841-4_4","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-030-78841-4_4","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Behavioral Synthesis for Hardware Security","raw_type":"book-chapter"},"type":"book-chapter","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5064996021","display_name":"Pranesh Santikellur","orcid":null},"institutions":[{"id":"https://openalex.org/I145894827","display_name":"Indian Institute of Technology Kharagpur","ror":"https://ror.org/03w5sq511","country_code":"IN","type":"education","lineage":["https://openalex.org/I145894827"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Pranesh Santikellur","raw_affiliation_strings":["Department of Computer Science and Engineering, Indian Institute of Technology, Kharagpur, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Indian Institute of Technology, Kharagpur, India","institution_ids":["https://openalex.org/I145894827"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5049426113","display_name":"Rajat Subhra Chakraborty","orcid":"https://orcid.org/0000-0003-3588-163X"},"institutions":[{"id":"https://openalex.org/I145894827","display_name":"Indian Institute of Technology Kharagpur","ror":"https://ror.org/03w5sq511","country_code":"IN","type":"education","lineage":["https://openalex.org/I145894827"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Rajat Subhra Chakraborty","raw_affiliation_strings":["Department of Computer Science and Engineering, Indian Institute of Technology, Kharagpur, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Indian Institute of Technology, Kharagpur, India","institution_ids":["https://openalex.org/I145894827"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5039442844","display_name":"Swarup Bhunia","orcid":"https://orcid.org/0000-0001-6082-6961"},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Swarup Bhunia","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Florida, Gainesville, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Florida, Gainesville, USA","institution_ids":["https://openalex.org/I33213144"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.5038,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.85728848,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"57","last_page":"69"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12495","display_name":"Electrostatic Discharge in Electronics","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7211341261863708},{"id":"https://openalex.org/keywords/obfuscation","display_name":"Obfuscation","score":0.6414201855659485},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.5261753797531128},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5253426432609558},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.5064970254898071},{"id":"https://openalex.org/keywords/control-flow","display_name":"Control flow","score":0.4929375648498535},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.48762837052345276},{"id":"https://openalex.org/keywords/control-logic","display_name":"Control logic","score":0.4657166004180908},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.44644662737846375},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3889305293560028},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.35599657893180847},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.3010711967945099},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.24205845594406128},{"id":"https://openalex.org/keywords/computer-security","display_name":"Computer security","score":0.10981076955795288},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.10369232296943665},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.09702867269515991},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.08957764506340027}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7211341261863708},{"id":"https://openalex.org/C40305131","wikidata":"https://www.wikidata.org/wiki/Q2616305","display_name":"Obfuscation","level":2,"score":0.6414201855659485},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.5261753797531128},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5253426432609558},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.5064970254898071},{"id":"https://openalex.org/C160191386","wikidata":"https://www.wikidata.org/wiki/Q868299","display_name":"Control flow","level":2,"score":0.4929375648498535},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.48762837052345276},{"id":"https://openalex.org/C2776350369","wikidata":"https://www.wikidata.org/wiki/Q843479","display_name":"Control logic","level":2,"score":0.4657166004180908},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.44644662737846375},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3889305293560028},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.35599657893180847},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.3010711967945099},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.24205845594406128},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.10981076955795288},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.10369232296943665},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.09702867269515991},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.08957764506340027}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/978-3-030-78841-4_4","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-3-030-78841-4_4","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Behavioral Synthesis for Hardware Security","raw_type":"book-chapter"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1988381220","https://openalex.org/W2042778609","https://openalex.org/W2047572892","https://openalex.org/W2103196322","https://openalex.org/W2125491202","https://openalex.org/W2126851641","https://openalex.org/W2564565181","https://openalex.org/W2566081789","https://openalex.org/W3150532282","https://openalex.org/W4230279121"],"related_works":["https://openalex.org/W1984298705","https://openalex.org/W2365114398","https://openalex.org/W2922751745","https://openalex.org/W1716153929","https://openalex.org/W4312497944","https://openalex.org/W2039527781","https://openalex.org/W2103196322","https://openalex.org/W2047558343","https://openalex.org/W2123887554","https://openalex.org/W4211193615"],"abstract_inverted_index":null,"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}