{"id":"https://openalex.org/W1847620574","doi":"https://doi.org/10.1007/978-1-4419-0263-4_2","title":"On-Chip Networks for Multicore Systems","display_name":"On-Chip Networks for Multicore Systems","publication_year":2009,"publication_date":"2009-01-01","ids":{"openalex":"https://openalex.org/W1847620574","doi":"https://doi.org/10.1007/978-1-4419-0263-4_2","mag":"1847620574"},"language":"en","primary_location":{"id":"doi:10.1007/978-1-4419-0263-4_2","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-1-4419-0263-4_2","pdf_url":null,"source":{"id":"https://openalex.org/S4210229257","display_name":"Integrated circuits and systems","issn_l":"1558-9412","issn":["1558-9412","1558-9420"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319965","host_organization_name":"Springer Nature","host_organization_lineage":["https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Integrated Circuits and Systems","raw_type":"book-chapter"},"type":"book-chapter","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5057413185","display_name":"Li-Shiuan Peh","orcid":"https://orcid.org/0000-0001-9010-6519"},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Li-Shiuan Peh","raw_affiliation_strings":["Princeton University, 08544, Princeton, New Jersey, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Princeton University, 08544, Princeton, New Jersey, USA","institution_ids":["https://openalex.org/I20089843"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063354509","display_name":"Stephen W. Keckler","orcid":"https://orcid.org/0000-0001-6701-6099"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Stephen W. Keckler","raw_affiliation_strings":["College of Natural Sciences, University of Texas, Austin, University Station 1, Austin, 78712-0233, U.S.A","The University of Texas at Austin, Austin, TX, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"College of Natural Sciences, University of Texas, Austin, University Station 1, Austin, 78712-0233, U.S.A","institution_ids":[]},{"raw_affiliation_string":"The University of Texas at Austin, Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102778960","display_name":"Sriram Vangal","orcid":"https://orcid.org/0000-0003-1548-9876"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sriram Vangal","raw_affiliation_strings":["Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5057413185"],"corresponding_institution_ids":["https://openalex.org/I20089843"],"apc_list":null,"apc_paid":null,"fwci":2.0218,"has_fulltext":false,"cited_by_count":17,"citation_normalized_percentile":{"value":0.87076702,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"35","last_page":"71"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9969000220298767,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9959999918937683,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/uniprocessor-system","display_name":"Uniprocessor system","score":0.845044732093811},{"id":"https://openalex.org/keywords/network-on-a-chip","display_name":"Network on a chip","score":0.6296342611312866},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.603901743888855},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.5625836849212646},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5539273619651794},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.5289081335067749},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5079053044319153},{"id":"https://openalex.org/keywords/moores-law","display_name":"Moore's law","score":0.487505167722702},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.4726601839065552},{"id":"https://openalex.org/keywords/router","display_name":"Router","score":0.47190576791763306},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.41977035999298096},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.29616856575012207},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.2352341115474701},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.19181624054908752},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.10173007845878601},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.08503586053848267}],"concepts":[{"id":"https://openalex.org/C79189994","wikidata":"https://www.wikidata.org/wiki/Q3488021","display_name":"Uniprocessor system","level":3,"score":0.845044732093811},{"id":"https://openalex.org/C128519102","wikidata":"https://www.wikidata.org/wiki/Q339554","display_name":"Network on a chip","level":2,"score":0.6296342611312866},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.603901743888855},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.5625836849212646},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5539273619651794},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.5289081335067749},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5079053044319153},{"id":"https://openalex.org/C206891323","wikidata":"https://www.wikidata.org/wiki/Q178655","display_name":"Moore's law","level":2,"score":0.487505167722702},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.4726601839065552},{"id":"https://openalex.org/C2775896111","wikidata":"https://www.wikidata.org/wiki/Q642560","display_name":"Router","level":2,"score":0.47190576791763306},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.41977035999298096},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.29616856575012207},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.2352341115474701},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.19181624054908752},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.10173007845878601},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.08503586053848267}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/978-1-4419-0263-4_2","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-1-4419-0263-4_2","pdf_url":null,"source":{"id":"https://openalex.org/S4210229257","display_name":"Integrated circuits and systems","issn_l":"1558-9412","issn":["1558-9412","1558-9420"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319965","host_organization_name":"Springer Nature","host_organization_lineage":["https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Integrated Circuits and Systems","raw_type":"book-chapter"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":52,"referenced_works":["https://openalex.org/W1501077214","https://openalex.org/W1550639219","https://openalex.org/W1573851380","https://openalex.org/W1973468635","https://openalex.org/W1978358211","https://openalex.org/W1979970276","https://openalex.org/W1984520032","https://openalex.org/W2001505646","https://openalex.org/W2011792082","https://openalex.org/W2017503457","https://openalex.org/W2022740893","https://openalex.org/W2035720033","https://openalex.org/W2055314364","https://openalex.org/W2059807497","https://openalex.org/W2065742943","https://openalex.org/W2086263221","https://openalex.org/W2096696871","https://openalex.org/W2097560795","https://openalex.org/W2099399959","https://openalex.org/W2099952176","https://openalex.org/W2099995085","https://openalex.org/W2100503336","https://openalex.org/W2100568203","https://openalex.org/W2109681980","https://openalex.org/W2115657122","https://openalex.org/W2119117967","https://openalex.org/W2120052218","https://openalex.org/W2122337686","https://openalex.org/W2126475076","https://openalex.org/W2134049183","https://openalex.org/W2134218813","https://openalex.org/W2143342758","https://openalex.org/W2145071646","https://openalex.org/W2147345262","https://openalex.org/W2148371977","https://openalex.org/W2151157308","https://openalex.org/W2153025112","https://openalex.org/W2155385791","https://openalex.org/W2155597158","https://openalex.org/W2159747318","https://openalex.org/W2171825402","https://openalex.org/W2540500304","https://openalex.org/W2544965182","https://openalex.org/W2611640388","https://openalex.org/W2914113053","https://openalex.org/W3003842159","https://openalex.org/W3141303489","https://openalex.org/W3142439385","https://openalex.org/W3150157207","https://openalex.org/W4234308027","https://openalex.org/W4239091598","https://openalex.org/W4239227582"],"related_works":["https://openalex.org/W2884494031","https://openalex.org/W2019683599","https://openalex.org/W2541055708","https://openalex.org/W2763650167","https://openalex.org/W1526558911","https://openalex.org/W3153161784","https://openalex.org/W2160936959","https://openalex.org/W4205403078","https://openalex.org/W62680457","https://openalex.org/W1847620574"],"abstract_inverted_index":null,"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":3},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}