{"id":"https://openalex.org/W71305360","doi":"https://doi.org/10.1007/978-0-387-74909-9_10","title":"Library Compatible Variational Delay Computation","display_name":"Library Compatible Variational Delay Computation","publication_year":2007,"publication_date":"2007-11-21","ids":{"openalex":"https://openalex.org/W71305360","doi":"https://doi.org/10.1007/978-0-387-74909-9_10","mag":"71305360"},"language":"en","primary_location":{"id":"doi:10.1007/978-0-387-74909-9_10","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-0-387-74909-9_10","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IFIP International Federation for Information Processing","raw_type":"book-chapter"},"type":"book-chapter","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5074463063","display_name":"Lu\u00eds Guerra e Silva","orcid":"https://orcid.org/0000-0001-5761-0131"},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]},{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["PT","US"],"is_corresponding":false,"raw_author_name":"Luis Guerra e Silva","raw_affiliation_strings":["Cadence Laboratories / INESC-ID IST, Tech. U. Lisbon, Lisbon, Portugal"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Cadence Laboratories / INESC-ID IST, Tech. U. Lisbon, Lisbon, Portugal","institution_ids":["https://openalex.org/I121345201","https://openalex.org/I66217453"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100891678","display_name":"Zhenhai Zhu","orcid":null},"institutions":[{"id":"https://openalex.org/I148283060","display_name":"Lawrence Berkeley National Laboratory","ror":"https://ror.org/02jbv0t02","country_code":"US","type":"facility","lineage":["https://openalex.org/I1330989302","https://openalex.org/I148283060","https://openalex.org/I39565521"]},{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Zhenhai Zhu","raw_affiliation_strings":["Cadence Berkeley Laboratories, Cadence Design Systems, 95134, San Jose, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Cadence Berkeley Laboratories, Cadence Design Systems, 95134, San Jose, CA, USA","institution_ids":["https://openalex.org/I148283060","https://openalex.org/I66217453"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060124540","display_name":"Joel Phillips","orcid":"https://orcid.org/0000-0002-3437-425X"},"institutions":[{"id":"https://openalex.org/I148283060","display_name":"Lawrence Berkeley National Laboratory","ror":"https://ror.org/02jbv0t02","country_code":"US","type":"facility","lineage":["https://openalex.org/I1330989302","https://openalex.org/I148283060","https://openalex.org/I39565521"]},{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Joel R. Phillips","raw_affiliation_strings":["Cadence Berkeley Laboratories, Cadence Design Systems, 95134, San Jose, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Cadence Berkeley Laboratories, Cadence Design Systems, 95134, San Jose, CA, USA","institution_ids":["https://openalex.org/I148283060","https://openalex.org/I66217453"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5052100713","display_name":"L. Miguel Silveira","orcid":"https://orcid.org/0000-0003-3542-229X"},"institutions":[{"id":"https://openalex.org/I121345201","display_name":"Instituto de Engenharia de Sistemas e Computadores Investiga\u00e7\u00e3o e Desenvolvimento","ror":"https://ror.org/04mqy3p58","country_code":"PT","type":"nonprofit","lineage":["https://openalex.org/I121345201","https://openalex.org/I4210125590"]},{"id":"https://openalex.org/I66217453","display_name":"Cadence Design Systems (United States)","ror":"https://ror.org/04w8xa018","country_code":"US","type":"company","lineage":["https://openalex.org/I66217453"]}],"countries":["PT","US"],"is_corresponding":false,"raw_author_name":"L. Miguel Silveira","raw_affiliation_strings":["Cadence Laboratories / INESC-ID IST, Tech. U. Lisbon, Lisbon, Portugal"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Cadence Laboratories / INESC-ID IST, Tech. U. Lisbon, Lisbon, Portugal","institution_ids":["https://openalex.org/I121345201","https://openalex.org/I66217453"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.02645503,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"157","last_page":"176"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7030579447746277},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.5836101174354553},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.5739139318466187},{"id":"https://openalex.org/keywords/static-timing-analysis","display_name":"Static timing analysis","score":0.5549589991569519},{"id":"https://openalex.org/keywords/delay-calculation","display_name":"Delay calculation","score":0.5430750846862793},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.5041288137435913},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.4389258623123169},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.43755099177360535},{"id":"https://openalex.org/keywords/context","display_name":"Context (archaeology)","score":0.43494921922683716},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.33704179525375366},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.28258657455444336},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.21460846066474915},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.17920276522636414},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15819388628005981}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7030579447746277},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.5836101174354553},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.5739139318466187},{"id":"https://openalex.org/C93682380","wikidata":"https://www.wikidata.org/wiki/Q2025226","display_name":"Static timing analysis","level":2,"score":0.5549589991569519},{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.5430750846862793},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5041288137435913},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.4389258623123169},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.43755099177360535},{"id":"https://openalex.org/C2779343474","wikidata":"https://www.wikidata.org/wiki/Q3109175","display_name":"Context (archaeology)","level":2,"score":0.43494921922683716},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.33704179525375366},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.28258657455444336},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.21460846066474915},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.17920276522636414},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15819388628005981},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/978-0-387-74909-9_10","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-0-387-74909-9_10","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IFIP International Federation for Information Processing","raw_type":"book-chapter"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1547254974","https://openalex.org/W1978981235","https://openalex.org/W2108816571","https://openalex.org/W2115477597","https://openalex.org/W2116444046","https://openalex.org/W2126564504","https://openalex.org/W2128744350","https://openalex.org/W2133268384","https://openalex.org/W2142896025","https://openalex.org/W2148507902","https://openalex.org/W2149599481","https://openalex.org/W2163262735","https://openalex.org/W2171961920","https://openalex.org/W4238688075","https://openalex.org/W4248062893"],"related_works":["https://openalex.org/W2100329931","https://openalex.org/W2145535176","https://openalex.org/W2158805860","https://openalex.org/W4229446324","https://openalex.org/W1570180536","https://openalex.org/W2117925677","https://openalex.org/W2110367374","https://openalex.org/W3131741930","https://openalex.org/W2003625360","https://openalex.org/W2544718775"],"abstract_inverted_index":null,"counts_by_year":[{"year":2018,"cited_by_count":1}],"updated_date":"2026-07-22T07:51:19.307946","created_date":"2025-10-10T00:00:00"}
