{"id":"https://openalex.org/W1598414776","doi":"https://doi.org/10.1007/978-0-387-72258-0_11","title":"Interconnect-aware Pipeline Synthesis for Array based Reconfigurable Architectures","display_name":"Interconnect-aware Pipeline Synthesis for Array based Reconfigurable Architectures","publication_year":2007,"publication_date":"2007-01-01","ids":{"openalex":"https://openalex.org/W1598414776","doi":"https://doi.org/10.1007/978-0-387-72258-0_11","mag":"1598414776"},"language":"en","primary_location":{"id":"doi:10.1007/978-0-387-72258-0_11","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-0-387-72258-0_11","pdf_url":null,"source":{"id":"https://openalex.org/S4210185096","display_name":"IFIP advances in information and communication technology","issn_l":"1868-422X","issn":["1868-422X","1868-4238"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IFIP Advances in Information and Communication Technology","raw_type":"book-chapter"},"type":"book-chapter","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5103540240","display_name":"Shanghua Gao","orcid":null},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Shanghua Gao","raw_affiliation_strings":["Department of Electronics Engineering, University of Tokyo"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronics Engineering, University of Tokyo","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102316024","display_name":"Kenshu Seto","orcid":null},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kenshu Seto","raw_affiliation_strings":["VLSI Design and Education Center, University of Tokyo"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"VLSI Design and Education Center, University of Tokyo","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103025045","display_name":"Satoshi Komatsu","orcid":"https://orcid.org/0000-0002-9180-9053"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Satoshi Komatsu","raw_affiliation_strings":["VLSI Design and Education Center, University of Tokyo"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"VLSI Design and Education Center, University of Tokyo","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5027837299","display_name":"Masahiro Fujita","orcid":"https://orcid.org/0000-0002-6516-4175"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masahiro Fujita","raw_affiliation_strings":["VLSI Design and Education Center, University of Tokyo"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"VLSI Design and Education Center, University of Tokyo","institution_ids":["https://openalex.org/I74801974"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I74801974"],"apc_list":null,"apc_paid":null,"fwci":0.5028,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.6900369,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"121","last_page":"134"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.8664507865905762},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.6711891889572144},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6629669666290283},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.6252946257591248},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.5997907519340515},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5902889370918274},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.5555313229560852},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.5452908873558044},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5132350921630859},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4336943030357361},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.4152792692184448},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.3386751711368561},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3212360143661499},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20990747213363647},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.11297178268432617},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.09276846051216125}],"concepts":[{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.8664507865905762},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.6711891889572144},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6629669666290283},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.6252946257591248},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5997907519340515},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5902889370918274},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.5555313229560852},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.5452908873558044},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5132350921630859},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4336943030357361},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.4152792692184448},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.3386751711368561},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3212360143661499},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20990747213363647},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.11297178268432617},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.09276846051216125},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/978-0-387-72258-0_11","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-0-387-72258-0_11","pdf_url":null,"source":{"id":"https://openalex.org/S4210185096","display_name":"IFIP advances in information and communication technology","issn_l":"1868-422X","issn":["1868-422X","1868-4238"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"IFIP Advances in Information and Communication Technology","raw_type":"book-chapter"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1965585119","https://openalex.org/W1987786682","https://openalex.org/W2070121263","https://openalex.org/W2093842169","https://openalex.org/W2105076302","https://openalex.org/W2108251415","https://openalex.org/W2116304229","https://openalex.org/W2123412205","https://openalex.org/W2129151831","https://openalex.org/W2140311411","https://openalex.org/W2158566102","https://openalex.org/W2168922271","https://openalex.org/W2171413119","https://openalex.org/W2296760900","https://openalex.org/W4234977208","https://openalex.org/W4235515009","https://openalex.org/W4239344586"],"related_works":["https://openalex.org/W2145339442","https://openalex.org/W4243305727","https://openalex.org/W3217774925","https://openalex.org/W2543290882","https://openalex.org/W4235515009","https://openalex.org/W2171413119","https://openalex.org/W1557016741","https://openalex.org/W2139708877","https://openalex.org/W1964556228","https://openalex.org/W2895905110"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
