{"id":"https://openalex.org/W621300437","doi":"https://doi.org/10.1007/978-0-387-69167-1","title":"SAT-Based Scalable Formal Verification Solutions","display_name":"SAT-Based Scalable Formal Verification Solutions","publication_year":2007,"publication_date":"2007-01-01","ids":{"openalex":"https://openalex.org/W621300437","doi":"https://doi.org/10.1007/978-0-387-69167-1","mag":"621300437"},"language":"en","primary_location":{"id":"doi:10.1007/978-0-387-69167-1","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-0-387-69167-1","pdf_url":null,"source":{"id":"https://openalex.org/S4210229257","display_name":"Integrated circuits and systems","issn_l":"1558-9412","issn":["1558-9412","1558-9420"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319965","host_organization_name":"Springer Nature","host_organization_lineage":["https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Series on Integrated Circuits and Systems","raw_type":"book"},"type":"book","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5085310714","display_name":"Malay Ganai","orcid":"https://orcid.org/0000-0003-0593-3419"},"institutions":[{"id":"https://openalex.org/I4210107353","display_name":"NEC (United States)","ror":"https://ror.org/01v791m31","country_code":"US","type":"company","lineage":["https://openalex.org/I118347220","https://openalex.org/I4210107353"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Malay K. Ganai","raw_affiliation_strings":["NEC Labs America, Princeton, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"NEC Labs America, Princeton, USA","institution_ids":["https://openalex.org/I4210107353"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5041231710","display_name":"Aarti Gupta","orcid":"https://orcid.org/0000-0001-6676-9400"},"institutions":[{"id":"https://openalex.org/I4210107353","display_name":"NEC (United States)","ror":"https://ror.org/01v791m31","country_code":"US","type":"company","lineage":["https://openalex.org/I118347220","https://openalex.org/I4210107353"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Aarti Gupta","raw_affiliation_strings":["NEC Labs America, Princeton, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"NEC Labs America, Princeton, USA","institution_ids":["https://openalex.org/I4210107353"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":3.2771,"has_fulltext":false,"cited_by_count":67,"citation_normalized_percentile":{"value":0.93103448,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":null,"last_page":null},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9969000220298767,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9958999752998352,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/functional-verification","display_name":"Functional verification","score":0.8111402988433838},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7069275379180908},{"id":"https://openalex.org/keywords/intelligent-verification","display_name":"Intelligent verification","score":0.6913424730300903},{"id":"https://openalex.org/keywords/verification","display_name":"Verification","score":0.616334080696106},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.5975819826126099},{"id":"https://openalex.org/keywords/high-level-verification","display_name":"High-level verification","score":0.5898213386535645},{"id":"https://openalex.org/keywords/scalability","display_name":"Scalability","score":0.5637783408164978},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.49828124046325684},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.4746689796447754},{"id":"https://openalex.org/keywords/formal-methods","display_name":"Formal methods","score":0.43440061807632446},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.43182283639907837},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.33179599046707153},{"id":"https://openalex.org/keywords/database","display_name":"Database","score":0.10422861576080322},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.06769338250160217},{"id":"https://openalex.org/keywords/software-development","display_name":"Software development","score":0.05977708101272583}],"concepts":[{"id":"https://openalex.org/C62460635","wikidata":"https://www.wikidata.org/wiki/Q5508853","display_name":"Functional verification","level":3,"score":0.8111402988433838},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7069275379180908},{"id":"https://openalex.org/C3406870","wikidata":"https://www.wikidata.org/wiki/Q6044160","display_name":"Intelligent verification","level":5,"score":0.6913424730300903},{"id":"https://openalex.org/C142284323","wikidata":"https://www.wikidata.org/wiki/Q7921323","display_name":"Verification","level":5,"score":0.616334080696106},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.5975819826126099},{"id":"https://openalex.org/C187250869","wikidata":"https://www.wikidata.org/wiki/Q5754573","display_name":"High-level verification","level":5,"score":0.5898213386535645},{"id":"https://openalex.org/C48044578","wikidata":"https://www.wikidata.org/wiki/Q727490","display_name":"Scalability","level":2,"score":0.5637783408164978},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.49828124046325684},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.4746689796447754},{"id":"https://openalex.org/C75606506","wikidata":"https://www.wikidata.org/wiki/Q1049183","display_name":"Formal methods","level":2,"score":0.43440061807632446},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.43182283639907837},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.33179599046707153},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.10422861576080322},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.06769338250160217},{"id":"https://openalex.org/C529173508","wikidata":"https://www.wikidata.org/wiki/Q638608","display_name":"Software development","level":3,"score":0.05977708101272583},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C186846655","wikidata":"https://www.wikidata.org/wiki/Q3398377","display_name":"Software construction","level":4,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1007/978-0-387-69167-1","is_oa":false,"landing_page_url":"https://doi.org/10.1007/978-0-387-69167-1","pdf_url":null,"source":{"id":"https://openalex.org/S4210229257","display_name":"Integrated circuits and systems","issn_l":"1558-9412","issn":["1558-9412","1558-9420"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319965","host_organization_name":"Springer Nature","host_organization_lineage":["https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Series on Integrated Circuits and Systems","raw_type":"book"},{"id":"pmh:oai:dial.uclouvain.be:ebook:5863","is_oa":false,"landing_page_url":"http://hdl.handle.net/2078/ebook:5863","pdf_url":null,"source":{"id":"https://openalex.org/S4306401902","display_name":"Digital Access to Libraries (Universit\u00e9 catholique de Louvain (UCL), l'Universit\u00e9 de Namur (UNamur) and the Universit\u00e9 Saint-Louis (USL-B))","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I95674353","host_organization_name":"UCLouvain","host_organization_lineage":["https://openalex.org/I95674353"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":""}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6399999856948853,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":1,"referenced_works":["https://openalex.org/W2496976557"],"related_works":["https://openalex.org/W2361881307","https://openalex.org/W2929969821","https://openalex.org/W4205300843","https://openalex.org/W2392047570","https://openalex.org/W3120172095","https://openalex.org/W3155012083","https://openalex.org/W2363848262","https://openalex.org/W2354470518","https://openalex.org/W2035244079","https://openalex.org/W2354050233"],"abstract_inverted_index":null,"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2024,"cited_by_count":4},{"year":2022,"cited_by_count":8},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":5},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":2},{"year":2014,"cited_by_count":6},{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":7}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}