{"id":"https://openalex.org/W1597805071","doi":"https://doi.org/10.1007/3-540-63465-7_231","title":"FPLD HDL synthesis employing high-level evolutionary algorithm optimisation","display_name":"FPLD HDL synthesis employing high-level evolutionary algorithm optimisation","publication_year":1997,"publication_date":"1997-01-01","ids":{"openalex":"https://openalex.org/W1597805071","doi":"https://doi.org/10.1007/3-540-63465-7_231","mag":"1597805071"},"language":"en","primary_location":{"id":"doi:10.1007/3-540-63465-7_231","is_oa":false,"landing_page_url":"https://doi.org/10.1007/3-540-63465-7_231","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},"type":"book-chapter","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5063003960","display_name":"Richard Bruce Maunder","orcid":null},"institutions":[{"id":"https://openalex.org/I154130895","display_name":"University of Auckland","ror":"https://ror.org/03b94tp07","country_code":"NZ","type":"education","lineage":["https://openalex.org/I154130895"]}],"countries":["NZ"],"is_corresponding":true,"raw_author_name":"R.Bruce Maunder","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, University of Auckland, 20 Symonds St., Auckland, New Zealand","[Department of Electrical & Electronic Engineering, University of Auckland, Auckland, New Zealand]"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, University of Auckland, 20 Symonds St., Auckland, New Zealand","institution_ids":["https://openalex.org/I154130895"]},{"raw_affiliation_string":"[Department of Electrical & Electronic Engineering, University of Auckland, Auckland, New Zealand]","institution_ids":["https://openalex.org/I154130895"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088166627","display_name":"Zoran Sal\u010di\u0107","orcid":"https://orcid.org/0000-0001-7714-9848"},"institutions":[{"id":"https://openalex.org/I154130895","display_name":"University of Auckland","ror":"https://ror.org/03b94tp07","country_code":"NZ","type":"education","lineage":["https://openalex.org/I154130895"]}],"countries":["NZ"],"is_corresponding":false,"raw_author_name":"Zoran A. Salcic","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, University of Auckland, 20 Symonds St., Auckland, New Zealand","[Department of Electrical & Electronic Engineering, University of Auckland, Auckland, New Zealand]"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, University of Auckland, 20 Symonds St., Auckland, New Zealand","institution_ids":["https://openalex.org/I154130895"]},{"raw_affiliation_string":"[Department of Electrical & Electronic Engineering, University of Auckland, Auckland, New Zealand]","institution_ids":["https://openalex.org/I154130895"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5065282240","display_name":"George Coghill","orcid":null},"institutions":[{"id":"https://openalex.org/I154130895","display_name":"University of Auckland","ror":"https://ror.org/03b94tp07","country_code":"NZ","type":"education","lineage":["https://openalex.org/I154130895"]}],"countries":["NZ"],"is_corresponding":false,"raw_author_name":"George G. Coghill","raw_affiliation_strings":["Department of Electrical and Electronic Engineering, University of Auckland, 20 Symonds St., Auckland, New Zealand","[Department of Electrical & Electronic Engineering, University of Auckland, Auckland, New Zealand]"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Electronic Engineering, University of Auckland, 20 Symonds St., Auckland, New Zealand","institution_ids":["https://openalex.org/I154130895"]},{"raw_affiliation_string":"[Department of Electrical & Electronic Engineering, University of Auckland, Auckland, New Zealand]","institution_ids":["https://openalex.org/I154130895"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5063003960"],"corresponding_institution_ids":["https://openalex.org/I154130895"],"apc_list":{"value":5000,"currency":"EUR","value_usd":5392},"apc_paid":null,"fwci":4.1361,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.93980234,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"265","last_page":"273"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12941","display_name":"Embedded Systems and FPGA Design","score":0.9363999962806702,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12941","display_name":"Embedded Systems and FPGA Design","score":0.9363999962806702,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.9161704778671265},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.7853530645370483},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.6671387553215027},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6662957668304443},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.507616400718689},{"id":"https://openalex.org/keywords/listing","display_name":"Listing (finance)","score":0.47718775272369385},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.45914220809936523},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.43062618374824524},{"id":"https://openalex.org/keywords/circuit-extraction","display_name":"Circuit extraction","score":0.42719486355781555},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.41256874799728394},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.35563787817955017},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.3199880123138428},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.31424063444137573},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.2627546191215515},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.22625663876533508},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.2211727499961853},{"id":"https://openalex.org/keywords/equivalent-circuit","display_name":"Equivalent circuit","score":0.2095504105091095},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19499385356903076},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1089906096458435}],"concepts":[{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.9161704778671265},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.7853530645370483},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.6671387553215027},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6662957668304443},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.507616400718689},{"id":"https://openalex.org/C2779820595","wikidata":"https://www.wikidata.org/wiki/Q798505","display_name":"Listing (finance)","level":2,"score":0.47718775272369385},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.45914220809936523},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.43062618374824524},{"id":"https://openalex.org/C26490066","wikidata":"https://www.wikidata.org/wiki/Q17006835","display_name":"Circuit extraction","level":4,"score":0.42719486355781555},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.41256874799728394},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.35563787817955017},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.3199880123138428},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.31424063444137573},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.2627546191215515},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.22625663876533508},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.2211727499961853},{"id":"https://openalex.org/C23572009","wikidata":"https://www.wikidata.org/wiki/Q964981","display_name":"Equivalent circuit","level":3,"score":0.2095504105091095},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19499385356903076},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1089906096458435},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C10138342","wikidata":"https://www.wikidata.org/wiki/Q43015","display_name":"Finance","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/3-540-63465-7_231","is_oa":false,"landing_page_url":"https://doi.org/10.1007/3-540-63465-7_231","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1533947422","https://openalex.org/W1584219532","https://openalex.org/W1639032689","https://openalex.org/W2035279479","https://openalex.org/W2106715551","https://openalex.org/W2154203817"],"related_works":["https://openalex.org/W2498204369","https://openalex.org/W2543290882","https://openalex.org/W2171856294","https://openalex.org/W1964556228","https://openalex.org/W2000778050","https://openalex.org/W2132665983","https://openalex.org/W2157874690","https://openalex.org/W2108495667","https://openalex.org/W2253173388","https://openalex.org/W2110242592"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
