{"id":"https://openalex.org/W1491697103","doi":"https://doi.org/10.1007/3-540-63465-7_230","title":"Automatic Mapping of Algorithms onto multiple FPGA-SRAM Modules","display_name":"Automatic Mapping of Algorithms onto multiple FPGA-SRAM Modules","publication_year":1997,"publication_date":"1997-01-01","ids":{"openalex":"https://openalex.org/W1491697103","doi":"https://doi.org/10.1007/3-540-63465-7_230","mag":"1491697103"},"language":"en","primary_location":{"id":"doi:10.1007/3-540-63465-7_230","is_oa":false,"landing_page_url":"https://doi.org/10.1007/3-540-63465-7_230","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},"type":"book-chapter","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5069397868","display_name":"S.J.B. Acock","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"S.J.B. Acock","raw_affiliation_strings":[],"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5108511642","display_name":"K.R. Dimond","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"K.R. Dimond","raw_affiliation_strings":[],"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5069397868"],"corresponding_institution_ids":[],"apc_list":{"value":5000,"currency":"EUR","value_usd":5392},"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.18453652,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"255","last_page":"264"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8644065260887146},{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.8057074546813965},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.789524495601654},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.781578004360199},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.6164698600769043},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.5392441153526306},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5240590572357178},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5125095844268799},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.47587648034095764},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.46401771903038025},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.4314323663711548},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4194566011428833},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3450459837913513}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8644065260887146},{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.8057074546813965},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.789524495601654},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.781578004360199},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.6164698600769043},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.5392441153526306},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5240590572357178},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5125095844268799},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.47587648034095764},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.46401771903038025},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.4314323663711548},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4194566011428833},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3450459837913513}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/3-540-63465-7_230","is_oa":false,"landing_page_url":"https://doi.org/10.1007/3-540-63465-7_230","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W107423272","https://openalex.org/W1969723618","https://openalex.org/W2010346244","https://openalex.org/W2037093958","https://openalex.org/W2086629796","https://openalex.org/W2095117703","https://openalex.org/W4234609313","https://openalex.org/W4236269389"],"related_works":["https://openalex.org/W2372022246","https://openalex.org/W2543290882","https://openalex.org/W2110818533","https://openalex.org/W4235515009","https://openalex.org/W2129508730","https://openalex.org/W1843355381","https://openalex.org/W1492116303","https://openalex.org/W2069295582","https://openalex.org/W2895905110","https://openalex.org/W2077870657"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
