{"id":"https://openalex.org/W1522075243","doi":"https://doi.org/10.1007/3-540-63465-7_228","title":"Technology-driven FSM partitioning for synthesis of large sequential circuits targeting lookup-table based FPGAs","display_name":"Technology-driven FSM partitioning for synthesis of large sequential circuits targeting lookup-table based FPGAs","publication_year":1997,"publication_date":"1997-01-01","ids":{"openalex":"https://openalex.org/W1522075243","doi":"https://doi.org/10.1007/3-540-63465-7_228","mag":"1522075243"},"language":"en","primary_location":{"id":"doi:10.1007/3-540-63465-7_228","is_oa":false,"landing_page_url":"https://doi.org/10.1007/3-540-63465-7_228","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},"type":"book-chapter","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5054490955","display_name":"K. Feske","orcid":null},"institutions":[{"id":"https://openalex.org/I4210095661","display_name":"Fraunhofer Institute for Integrated Circuits IIS, Division Engineering of Adaptive Systems EAS","ror":"https://ror.org/00s5yp124","country_code":"DE","type":"facility","lineage":["https://openalex.org/I4210095661","https://openalex.org/I4210124274","https://openalex.org/I4923324"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Klaus Feske","raw_affiliation_strings":["Department EAS Dresden, FhG IIS Erlangen, Dresden, Germany"],"affiliations":[{"raw_affiliation_string":"Department EAS Dresden, FhG IIS Erlangen, Dresden, Germany","institution_ids":["https://openalex.org/I4210095661"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5064339332","display_name":"Sven Mulka","orcid":null},"institutions":[{"id":"https://openalex.org/I4210095661","display_name":"Fraunhofer Institute for Integrated Circuits IIS, Division Engineering of Adaptive Systems EAS","ror":"https://ror.org/00s5yp124","country_code":"DE","type":"facility","lineage":["https://openalex.org/I4210095661","https://openalex.org/I4210124274","https://openalex.org/I4923324"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Sven Mulka","raw_affiliation_strings":["Department EAS Dresden, FhG IIS Erlangen, Dresden, Germany"],"affiliations":[{"raw_affiliation_string":"Department EAS Dresden, FhG IIS Erlangen, Dresden, Germany","institution_ids":["https://openalex.org/I4210095661"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5107857395","display_name":"M. Koegst","orcid":null},"institutions":[{"id":"https://openalex.org/I4210095661","display_name":"Fraunhofer Institute for Integrated Circuits IIS, Division Engineering of Adaptive Systems EAS","ror":"https://ror.org/00s5yp124","country_code":"DE","type":"facility","lineage":["https://openalex.org/I4210095661","https://openalex.org/I4210124274","https://openalex.org/I4923324"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Manfred Koegst","raw_affiliation_strings":["Department EAS Dresden, FhG IIS Erlangen, Dresden, Germany"],"affiliations":[{"raw_affiliation_string":"Department EAS Dresden, FhG IIS Erlangen, Dresden, Germany","institution_ids":["https://openalex.org/I4210095661"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109042199","display_name":"G\u00fcnte Elst","orcid":null},"institutions":[{"id":"https://openalex.org/I4210095661","display_name":"Fraunhofer Institute for Integrated Circuits IIS, Division Engineering of Adaptive Systems EAS","ror":"https://ror.org/00s5yp124","country_code":"DE","type":"facility","lineage":["https://openalex.org/I4210095661","https://openalex.org/I4210124274","https://openalex.org/I4923324"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"G\u00fcnte Elst","raw_affiliation_strings":["Department EAS Dresden, FhG IIS Erlangen, Dresden, Germany"],"affiliations":[{"raw_affiliation_string":"Department EAS Dresden, FhG IIS Erlangen, Dresden, Germany","institution_ids":["https://openalex.org/I4210095661"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5054490955"],"corresponding_institution_ids":["https://openalex.org/I4210095661"],"apc_list":{"value":5000,"currency":"EUR","value_usd":5392},"apc_paid":null,"fwci":0.6087,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.60422535,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"235","last_page":"244"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.9161218404769897},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8556302785873413},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8273205757141113},{"id":"https://openalex.org/keywords/finite-state-machine","display_name":"Finite-state machine","score":0.7016960978507996},{"id":"https://openalex.org/keywords/table","display_name":"Table (database)","score":0.6419639587402344},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5842016935348511},{"id":"https://openalex.org/keywords/state","display_name":"State (computer science)","score":0.5222309827804565},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4345552623271942},{"id":"https://openalex.org/keywords/encoding","display_name":"Encoding (memory)","score":0.43153882026672363},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.4260004460811615},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4151616394519806},{"id":"https://openalex.org/keywords/data-flow-analysis","display_name":"Data-flow analysis","score":0.41170045733451843},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4104590117931366},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3769285976886749},{"id":"https://openalex.org/keywords/data-flow-diagram","display_name":"Data flow diagram","score":0.3741515874862671},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3574376404285431},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.32912278175354004},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.2490186095237732},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.10040506720542908},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.0757153332233429},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.06759670376777649},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.06223610043525696}],"concepts":[{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.9161218404769897},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8556302785873413},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8273205757141113},{"id":"https://openalex.org/C167822520","wikidata":"https://www.wikidata.org/wiki/Q176452","display_name":"Finite-state machine","level":2,"score":0.7016960978507996},{"id":"https://openalex.org/C45235069","wikidata":"https://www.wikidata.org/wiki/Q278425","display_name":"Table (database)","level":2,"score":0.6419639587402344},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5842016935348511},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.5222309827804565},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4345552623271942},{"id":"https://openalex.org/C125411270","wikidata":"https://www.wikidata.org/wiki/Q18653","display_name":"Encoding (memory)","level":2,"score":0.43153882026672363},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.4260004460811615},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4151616394519806},{"id":"https://openalex.org/C88468194","wikidata":"https://www.wikidata.org/wiki/Q1172416","display_name":"Data-flow analysis","level":3,"score":0.41170045733451843},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4104590117931366},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3769285976886749},{"id":"https://openalex.org/C489000","wikidata":"https://www.wikidata.org/wiki/Q747385","display_name":"Data flow diagram","level":2,"score":0.3741515874862671},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3574376404285431},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.32912278175354004},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.2490186095237732},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.10040506720542908},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0757153332233429},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.06759670376777649},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.06223610043525696},{"id":"https://openalex.org/C124101348","wikidata":"https://www.wikidata.org/wiki/Q172491","display_name":"Data mining","level":1,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1007/3-540-63465-7_228","is_oa":false,"landing_page_url":"https://doi.org/10.1007/3-540-63465-7_228","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},{"id":"pmh:oai:publica.fraunhofer.de:publica/329129","is_oa":false,"landing_page_url":"https://publica.fraunhofer.de/handle/publica/329129","pdf_url":null,"source":{"id":"https://openalex.org/S4306400318","display_name":"Fraunhofer-Publica (Fraunhofer-Gesellschaft)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4923324","host_organization_name":"Fraunhofer-Gesellschaft","host_organization_lineage":["https://openalex.org/I4923324"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"conference paper"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.5699999928474426}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W142838967","https://openalex.org/W1511688816","https://openalex.org/W1582261418","https://openalex.org/W2051817701","https://openalex.org/W2072740520","https://openalex.org/W2094460881","https://openalex.org/W2129230914","https://openalex.org/W2130232632","https://openalex.org/W2154204225","https://openalex.org/W2478397245","https://openalex.org/W6630623413"],"related_works":["https://openalex.org/W59945861","https://openalex.org/W2155289750","https://openalex.org/W2159724425","https://openalex.org/W4231267350","https://openalex.org/W2117956479","https://openalex.org/W2086821903","https://openalex.org/W2053477566","https://openalex.org/W4255564979","https://openalex.org/W1551967076","https://openalex.org/W2151163382"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
