{"id":"https://openalex.org/W1512463266","doi":"https://doi.org/10.1007/3-540-61730-2_47","title":"FPGA design migration: Some remarks","display_name":"FPGA design migration: Some remarks","publication_year":1996,"publication_date":"1996-01-01","ids":{"openalex":"https://openalex.org/W1512463266","doi":"https://doi.org/10.1007/3-540-61730-2_47","mag":"1512463266"},"language":"en","primary_location":{"id":"doi:10.1007/3-540-61730-2_47","is_oa":false,"landing_page_url":"https://doi.org/10.1007/3-540-61730-2_47","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},"type":"book-chapter","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5063949853","display_name":"V. Tchoumatchenko","orcid":null},"institutions":[{"id":"https://openalex.org/I31151848","display_name":"Technical University of Sofia","ror":"https://ror.org/052prhs50","country_code":"BG","type":"education","lineage":["https://openalex.org/I31151848"]}],"countries":["BG"],"is_corresponding":false,"raw_author_name":"V. Tchoumatchenko","raw_affiliation_strings":["Dept. of Electronics, Technical University, 1756, Sofia, Bulgaria","Dept. of Electronics, Technical University, Sofia, Bulgaria"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Electronics, Technical University, 1756, Sofia, Bulgaria","institution_ids":["https://openalex.org/I31151848"]},{"raw_affiliation_string":"Dept. of Electronics, Technical University, Sofia, Bulgaria","institution_ids":["https://openalex.org/I31151848"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5083891844","display_name":"T. Vassileva","orcid":null},"institutions":[{"id":"https://openalex.org/I31151848","display_name":"Technical University of Sofia","ror":"https://ror.org/052prhs50","country_code":"BG","type":"education","lineage":["https://openalex.org/I31151848"]}],"countries":["BG"],"is_corresponding":false,"raw_author_name":"T. Vassileva","raw_affiliation_strings":["Dept. of Electronics, Technical University, 1756, Sofia, Bulgaria","Dept. of Electronics, Technical University, Sofia, Bulgaria"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Electronics, Technical University, 1756, Sofia, Bulgaria","institution_ids":["https://openalex.org/I31151848"]},{"raw_affiliation_string":"Dept. of Electronics, Technical University, Sofia, Bulgaria","institution_ids":["https://openalex.org/I31151848"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031451721","display_name":"R. V. Ribas","orcid":"https://orcid.org/0000-0002-4081-125X"},"institutions":[{"id":"https://openalex.org/I31151848","display_name":"Technical University of Sofia","ror":"https://ror.org/052prhs50","country_code":"BG","type":"education","lineage":["https://openalex.org/I31151848"]},{"id":"https://openalex.org/I4210087012","display_name":"Techniques of Informatics and Microelectronics for Integrated Systems Architecture","ror":"https://ror.org/000063q30","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210159245","https://openalex.org/I899635006","https://openalex.org/I899635006"]}],"countries":["BG","FR"],"is_corresponding":false,"raw_author_name":"R. Ribas","raw_affiliation_strings":["Dept. of Electronics, Technical University, 1756, Sofia, Bulgaria","TIMA laboratory, 46 F\u00e9lix Viallet, F38031, Grenoble, France","TIMA laboratory, Grenoble, France","Dept. of Electronics, Technical University, Sofia, Bulgaria"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Electronics, Technical University, 1756, Sofia, Bulgaria","institution_ids":["https://openalex.org/I31151848"]},{"raw_affiliation_string":"TIMA laboratory, 46 F\u00e9lix Viallet, F38031, Grenoble, France","institution_ids":["https://openalex.org/I4210087012"]},{"raw_affiliation_string":"TIMA laboratory, Grenoble, France","institution_ids":["https://openalex.org/I4210087012"]},{"raw_affiliation_string":"Dept. of Electronics, Technical University, Sofia, Bulgaria","institution_ids":["https://openalex.org/I31151848"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111216671","display_name":"A. Guyot","orcid":null},"institutions":[{"id":"https://openalex.org/I31151848","display_name":"Technical University of Sofia","ror":"https://ror.org/052prhs50","country_code":"BG","type":"education","lineage":["https://openalex.org/I31151848"]},{"id":"https://openalex.org/I4210087012","display_name":"Techniques of Informatics and Microelectronics for Integrated Systems Architecture","ror":"https://ror.org/000063q30","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210159245","https://openalex.org/I899635006","https://openalex.org/I899635006"]}],"countries":["BG","FR"],"is_corresponding":false,"raw_author_name":"A. Guyot","raw_affiliation_strings":["Dept. of Electronics, Technical University, 1756, Sofia, Bulgaria","TIMA laboratory, 46 F\u00e9lix Viallet, F38031, Grenoble, France","Dept. of Electronics, Technical University, Sofia, Bulgaria","TIMA laboratory, Grenoble, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Electronics, Technical University, 1756, Sofia, Bulgaria","institution_ids":["https://openalex.org/I31151848"]},{"raw_affiliation_string":"TIMA laboratory, 46 F\u00e9lix Viallet, F38031, Grenoble, France","institution_ids":["https://openalex.org/I4210087012"]},{"raw_affiliation_string":"Dept. of Electronics, Technical University, Sofia, Bulgaria","institution_ids":["https://openalex.org/I31151848"]},{"raw_affiliation_string":"TIMA laboratory, Grenoble, France","institution_ids":["https://openalex.org/I4210087012"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":{"value":5000,"currency":"EUR","value_usd":5392},"apc_paid":null,"fwci":1.9436,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.84413035,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"405","last_page":"409"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8616669178009033},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7752648591995239},{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.6841448545455933},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5613092184066772},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.48501893877983093},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.474331796169281},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4683254063129425},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.43658897280693054},{"id":"https://openalex.org/keywords/relation","display_name":"Relation (database)","score":0.43011674284935},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.40025776624679565},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3498472273349762},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3492752015590668},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.33668431639671326},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.26518505811691284},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.18556350469589233}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8616669178009033},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7752648591995239},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.6841448545455933},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5613092184066772},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.48501893877983093},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.474331796169281},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4683254063129425},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.43658897280693054},{"id":"https://openalex.org/C25343380","wikidata":"https://www.wikidata.org/wiki/Q277521","display_name":"Relation (database)","level":2,"score":0.43011674284935},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.40025776624679565},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3498472273349762},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3492752015590668},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.33668431639671326},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.26518505811691284},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.18556350469589233},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C77088390","wikidata":"https://www.wikidata.org/wiki/Q8513","display_name":"Database","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/3-540-61730-2_47","is_oa":false,"landing_page_url":"https://doi.org/10.1007/3-540-61730-2_47","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.7300000190734863,"id":"https://metadata.un.org/sdg/10","display_name":"Reduced inequalities"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W610250046","https://openalex.org/W1510109757","https://openalex.org/W2020530545","https://openalex.org/W2050652156"],"related_works":["https://openalex.org/W2337636225","https://openalex.org/W1512285683","https://openalex.org/W2197466303","https://openalex.org/W2151236218","https://openalex.org/W2187918628","https://openalex.org/W4234601000","https://openalex.org/W1965232212","https://openalex.org/W2534453537","https://openalex.org/W1986441503","https://openalex.org/W2139569078"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}