{"id":"https://openalex.org/W1751928709","doi":"https://doi.org/10.1007/3-540-61730-2_38","title":"ASIC design and FPGA design: A unified design methodology applied to different technologies","display_name":"ASIC design and FPGA design: A unified design methodology applied to different technologies","publication_year":1996,"publication_date":"1996-01-01","ids":{"openalex":"https://openalex.org/W1751928709","doi":"https://doi.org/10.1007/3-540-61730-2_38","mag":"1751928709"},"language":"en","primary_location":{"id":"doi:10.1007/3-540-61730-2_38","is_oa":false,"landing_page_url":"https://doi.org/10.1007/3-540-61730-2_38","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},"type":"book-chapter","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5037046601","display_name":"A. Balboni","orcid":"https://orcid.org/0009-0003-8872-976X"},"institutions":[{"id":"https://openalex.org/I2799464224","display_name":"Italtel (Italy)","ror":"https://ror.org/012ae7p27","country_code":"IT","type":"company","lineage":["https://openalex.org/I2799464224"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"Alessandro Balboni","raw_affiliation_strings":["ITALTEL SpA Central R&D Catselletto di Settimo Mil., 20019, Milan, Italy","ITALTEL SpA Central R&D Catselletto di Settimo Mil"],"affiliations":[{"raw_affiliation_string":"ITALTEL SpA Central R&D Catselletto di Settimo Mil., 20019, Milan, Italy","institution_ids":["https://openalex.org/I2799464224"]},{"raw_affiliation_string":"ITALTEL SpA Central R&D Catselletto di Settimo Mil","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5008093261","display_name":"Loris Valenti","orcid":null},"institutions":[{"id":"https://openalex.org/I2799464224","display_name":"Italtel (Italy)","ror":"https://ror.org/012ae7p27","country_code":"IT","type":"company","lineage":["https://openalex.org/I2799464224"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Loris Valenti","raw_affiliation_strings":["ITALTEL SpA Central R&D Catselletto di Settimo Mil., 20019, Milan, Italy","ITALTEL SpA Central R&D Catselletto di Settimo Mil"],"affiliations":[{"raw_affiliation_string":"ITALTEL SpA Central R&D Catselletto di Settimo Mil., 20019, Milan, Italy","institution_ids":["https://openalex.org/I2799464224"]},{"raw_affiliation_string":"ITALTEL SpA Central R&D Catselletto di Settimo Mil","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5037046601"],"corresponding_institution_ids":["https://openalex.org/I2799464224"],"apc_list":{"value":5000,"currency":"EUR","value_usd":5392},"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.19151421,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"356","last_page":"360"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.7008000016212463,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.7008000016212463,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.7002999782562256,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.6988999843597412,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.885718822479248},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.7976002097129822},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.79332435131073},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6007152795791626},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5781635046005249},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5258619785308838},{"id":"https://openalex.org/keywords/design-technology","display_name":"Design technology","score":0.4902665913105011},{"id":"https://openalex.org/keywords/independence","display_name":"Independence (probability theory)","score":0.48334309458732605},{"id":"https://openalex.org/keywords/design-methods","display_name":"Design methods","score":0.4175170660018921},{"id":"https://openalex.org/keywords/systems-engineering","display_name":"Systems engineering","score":0.3200097680091858},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3098219335079193},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.07236301898956299}],"concepts":[{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.885718822479248},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.7976002097129822},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.79332435131073},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6007152795791626},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5781635046005249},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5258619785308838},{"id":"https://openalex.org/C179737136","wikidata":"https://www.wikidata.org/wiki/Q5264382","display_name":"Design technology","level":2,"score":0.4902665913105011},{"id":"https://openalex.org/C35651441","wikidata":"https://www.wikidata.org/wiki/Q625303","display_name":"Independence (probability theory)","level":2,"score":0.48334309458732605},{"id":"https://openalex.org/C138852830","wikidata":"https://www.wikidata.org/wiki/Q2292993","display_name":"Design methods","level":2,"score":0.4175170660018921},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.3200097680091858},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3098219335079193},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.07236301898956299},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/3-540-61730-2_38","is_oa":false,"landing_page_url":"https://doi.org/10.1007/3-540-61730-2_38","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.41999998688697815,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W1485756991","https://openalex.org/W2376218453","https://openalex.org/W2984236338","https://openalex.org/W1751928709","https://openalex.org/W2390081926","https://openalex.org/W2669791463","https://openalex.org/W2330220111","https://openalex.org/W2364797485","https://openalex.org/W3027746919","https://openalex.org/W2543997268"],"abstract_inverted_index":null,"counts_by_year":[{"year":2023,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
