{"id":"https://openalex.org/W1608572506","doi":"https://doi.org/10.1007/3-540-60294-1_93","title":"The design of a new FPGA architecture","display_name":"The design of a new FPGA architecture","publication_year":1995,"publication_date":"1995-01-01","ids":{"openalex":"https://openalex.org/W1608572506","doi":"https://doi.org/10.1007/3-540-60294-1_93","mag":"1608572506"},"language":"en","primary_location":{"id":"doi:10.1007/3-540-60294-1_93","is_oa":false,"landing_page_url":"https://doi.org/10.1007/3-540-60294-1_93","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},"type":"book-chapter","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5038639809","display_name":"A. Stansfield","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Anthony Stansfield","raw_affiliation_strings":["SRP/PACT 10 Priory Road, BS8 1TU, Bristol"],"affiliations":[{"raw_affiliation_string":"SRP/PACT 10 Priory Road, BS8 1TU, Bristol","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5010806343","display_name":"Ian Page","orcid":null},"institutions":[{"id":"https://openalex.org/I40120149","display_name":"University of Oxford","ror":"https://ror.org/052gg0110","country_code":"GB","type":"education","lineage":["https://openalex.org/I40120149"]},{"id":"https://openalex.org/I4210146719","display_name":"Central Compilation & Translation Bureau","ror":"https://ror.org/0411yf357","country_code":"CN","type":"nonprofit","lineage":["https://openalex.org/I4210146719"]}],"countries":["CN","GB"],"is_corresponding":false,"raw_author_name":"Ian Page","raw_affiliation_strings":["Group Leader,\n        Hardware Compilation Research Group, Oxford University, Computing Laboratory, Parks Road, OX1 3QD, Oxford"],"affiliations":[{"raw_affiliation_string":"Group Leader,\n        Hardware Compilation Research Group, Oxford University, Computing Laboratory, Parks Road, OX1 3QD, Oxford","institution_ids":["https://openalex.org/I4210146719","https://openalex.org/I40120149"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5038639809"],"corresponding_institution_ids":[],"apc_list":{"value":5000,"currency":"EUR","value_usd":5392},"apc_paid":null,"fwci":2.2621,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.87599364,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"14"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9620000123977661,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9620000123977661,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9014000296592712,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.919631838798523},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8064868450164795},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.7061638832092285},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.7048174738883972},{"id":"https://openalex.org/keywords/programmable-array-logic","display_name":"Programmable Array Logic","score":0.5742639899253845},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.52679044008255},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5065299272537231},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.4920046031475067},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.47685492038726807},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.46992456912994385},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.4372304379940033},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.4104980230331421},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.25038886070251465},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.16397708654403687},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.0841442346572876},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.08379840850830078}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.919631838798523},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8064868450164795},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.7061638832092285},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.7048174738883972},{"id":"https://openalex.org/C113323844","wikidata":"https://www.wikidata.org/wiki/Q1378651","display_name":"Programmable Array Logic","level":5,"score":0.5742639899253845},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.52679044008255},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5065299272537231},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.4920046031475067},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.47685492038726807},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.46992456912994385},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.4372304379940033},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.4104980230331421},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.25038886070251465},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.16397708654403687},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0841442346572876},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.08379840850830078},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1007/3-540-60294-1_93","is_oa":false,"landing_page_url":"https://doi.org/10.1007/3-540-60294-1_93","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.47.8674","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.47.8674","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"ftp://ftp.comlab.ox.ac.uk/pub/Documents/techpapers/Ian.Page/cam95.ps","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/11","display_name":"Sustainable cities and communities","score":0.550000011920929}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W44516245","https://openalex.org/W101337918","https://openalex.org/W2113764809","https://openalex.org/W6604118845"],"related_works":["https://openalex.org/W2376859467","https://openalex.org/W2534453537","https://openalex.org/W1541210136","https://openalex.org/W3120977519","https://openalex.org/W2145701142","https://openalex.org/W1821888792","https://openalex.org/W2057745131","https://openalex.org/W2538721963","https://openalex.org/W2115587156","https://openalex.org/W2103012267"],"abstract_inverted_index":null,"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}