{"id":"https://openalex.org/W1606210480","doi":"https://doi.org/10.1007/3-540-58419-6_104","title":"Continuous interconnect provides solution to density/performance trade-off in programmable logic","display_name":"Continuous interconnect provides solution to density/performance trade-off in programmable logic","publication_year":1994,"publication_date":"1994-01-01","ids":{"openalex":"https://openalex.org/W1606210480","doi":"https://doi.org/10.1007/3-540-58419-6_104","mag":"1606210480"},"language":"en","primary_location":{"id":"doi:10.1007/3-540-58419-6_104","is_oa":false,"landing_page_url":"https://doi.org/10.1007/3-540-58419-6_104","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},"type":"book-chapter","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5021334240","display_name":"Nigel Toon","orcid":null},"institutions":[{"id":"https://openalex.org/I22433950","display_name":"Altera (United States)","ror":"https://ror.org/017b7j426","country_code":"US","type":"company","lineage":["https://openalex.org/I22433950"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Nigel Toon","raw_affiliation_strings":["European Marketing Manager,\n        Altera Corporation, USA","Altera Corporation#TAB#"],"affiliations":[{"raw_affiliation_string":"European Marketing Manager,\n        Altera Corporation, USA","institution_ids":["https://openalex.org/I22433950"]},{"raw_affiliation_string":"Altera Corporation#TAB#","institution_ids":["https://openalex.org/I22433950"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5021334240"],"corresponding_institution_ids":["https://openalex.org/I22433950"],"apc_list":{"value":5000,"currency":"EUR","value_usd":5392},"apc_paid":null,"fwci":2.1847,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.86298851,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"292","last_page":"294"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9959999918937683,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9959999918937683,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9876999855041504,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9854000210762024,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/simple-programmable-logic-device","display_name":"Simple programmable logic device","score":0.8178489804267883},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.8124452829360962},{"id":"https://openalex.org/keywords/erasable-programmable-logic-device","display_name":"Erasable programmable logic device","score":0.7885004878044128},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.7461124062538147},{"id":"https://openalex.org/keywords/programmable-array-logic","display_name":"Programmable Array Logic","score":0.7158610224723816},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6980078816413879},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.6057022213935852},{"id":"https://openalex.org/keywords/macrocell-array","display_name":"Macrocell array","score":0.6008810997009277},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4505966603755951},{"id":"https://openalex.org/keywords/complex-programmable-logic-device","display_name":"Complex programmable logic device","score":0.4226749837398529},{"id":"https://openalex.org/keywords/programmable-logic-controller","display_name":"Programmable logic controller","score":0.41182103753089905},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.404821515083313},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.401639461517334},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.39687415957450867},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3712466061115265},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3573833107948303},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13123571872711182},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.12048012018203735},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.09904950857162476},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.06271782517433167}],"concepts":[{"id":"https://openalex.org/C34370810","wikidata":"https://www.wikidata.org/wiki/Q3961319","display_name":"Simple programmable logic device","level":5,"score":0.8178489804267883},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.8124452829360962},{"id":"https://openalex.org/C110050671","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Erasable programmable logic device","level":5,"score":0.7885004878044128},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.7461124062538147},{"id":"https://openalex.org/C113323844","wikidata":"https://www.wikidata.org/wiki/Q1378651","display_name":"Programmable Array Logic","level":5,"score":0.7158610224723816},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6980078816413879},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.6057022213935852},{"id":"https://openalex.org/C142278197","wikidata":"https://www.wikidata.org/wiki/Q4284934","display_name":"Macrocell array","level":5,"score":0.6008810997009277},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4505966603755951},{"id":"https://openalex.org/C128315158","wikidata":"https://www.wikidata.org/wiki/Q1063858","display_name":"Complex programmable logic device","level":2,"score":0.4226749837398529},{"id":"https://openalex.org/C37374048","wikidata":"https://www.wikidata.org/wiki/Q188674","display_name":"Programmable logic controller","level":2,"score":0.41182103753089905},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.404821515083313},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.401639461517334},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.39687415957450867},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3712466061115265},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3573833107948303},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13123571872711182},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.12048012018203735},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.09904950857162476},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.06271782517433167}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/3-540-58419-6_104","is_oa":false,"landing_page_url":"https://doi.org/10.1007/3-540-58419-6_104","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W1528933814","https://openalex.org/W3117015220","https://openalex.org/W3013792460","https://openalex.org/W133576369","https://openalex.org/W1904803855","https://openalex.org/W3022525969","https://openalex.org/W2376859467","https://openalex.org/W4389045693","https://openalex.org/W2054740893","https://openalex.org/W2764789987"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}