{"id":"https://openalex.org/W1450750664","doi":"https://doi.org/10.1007/3-540-57091-8_38","title":"A real-time kernel \u2014 Rapid prototyping with VHDL and FPGAs","display_name":"A real-time kernel \u2014 Rapid prototyping with VHDL and FPGAs","publication_year":1993,"publication_date":"1993-01-01","ids":{"openalex":"https://openalex.org/W1450750664","doi":"https://doi.org/10.1007/3-540-57091-8_38","mag":"1450750664"},"language":"en","primary_location":{"id":"doi:10.1007/3-540-57091-8_38","is_oa":false,"landing_page_url":"https://doi.org/10.1007/3-540-57091-8_38","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},"type":"book-chapter","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5013051481","display_name":"Lennart Lindh","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Lennart Lindh","raw_affiliation_strings":["CUS Institute, University of Eksilstuna/V\u00e4ster\u00e5s, P.O.Box 11, 72103, V\u00e4ster\u00e5s, Sweden","University of Eksilstuna/V\u00e4ster\u00e5s"],"affiliations":[{"raw_affiliation_string":"CUS Institute, University of Eksilstuna/V\u00e4ster\u00e5s, P.O.Box 11, 72103, V\u00e4ster\u00e5s, Sweden","institution_ids":[]},{"raw_affiliation_string":"University of Eksilstuna/V\u00e4ster\u00e5s","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110182829","display_name":"Klaus D. M\u00fcller-Glaser","orcid":null},"institutions":[{"id":"https://openalex.org/I181369854","display_name":"Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg","ror":"https://ror.org/00f7hpc57","country_code":"DE","type":"education","lineage":["https://openalex.org/I181369854"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Klaus M\u00fcller-Glaser","raw_affiliation_strings":["Institute for Computer Aided Circuit Design, University of Erlangen/N\u00fcrnberg, Cauerstr.6, 8520, Erlangen, Germany","University of Erlangen\u2010N\u00fcrnberg ,"],"affiliations":[{"raw_affiliation_string":"Institute for Computer Aided Circuit Design, University of Erlangen/N\u00fcrnberg, Cauerstr.6, 8520, Erlangen, Germany","institution_ids":["https://openalex.org/I181369854"]},{"raw_affiliation_string":"University of Erlangen\u2010N\u00fcrnberg ,","institution_ids":["https://openalex.org/I181369854"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044216431","display_name":"Hans Rauch","orcid":null},"institutions":[{"id":"https://openalex.org/I181369854","display_name":"Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg","ror":"https://ror.org/00f7hpc57","country_code":"DE","type":"education","lineage":["https://openalex.org/I181369854"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Hans Rauch","raw_affiliation_strings":["Institute for Computer Aided Circuit Design, University of Erlangen/N\u00fcrnberg, Cauerstr.6, 8520, Erlangen, Germany","University of Erlangen\u2010N\u00fcrnberg ,"],"affiliations":[{"raw_affiliation_string":"Institute for Computer Aided Circuit Design, University of Erlangen/N\u00fcrnberg, Cauerstr.6, 8520, Erlangen, Germany","institution_ids":["https://openalex.org/I181369854"]},{"raw_affiliation_string":"University of Erlangen\u2010N\u00fcrnberg ,","institution_ids":["https://openalex.org/I181369854"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5016032123","display_name":"Frank Stanischewski","orcid":null},"institutions":[{"id":"https://openalex.org/I181369854","display_name":"Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg","ror":"https://ror.org/00f7hpc57","country_code":"DE","type":"education","lineage":["https://openalex.org/I181369854"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Frank Stanischewski","raw_affiliation_strings":["Institute of Computer Science (IMMD 3), University of Erlangen/N\u00fcrnberg, Martensstr.3, 8520, Erlangen, Germany","University of Erlangen\u2010N\u00fcrnberg ,"],"affiliations":[{"raw_affiliation_string":"Institute of Computer Science (IMMD 3), University of Erlangen/N\u00fcrnberg, Martensstr.3, 8520, Erlangen, Germany","institution_ids":["https://openalex.org/I181369854"]},{"raw_affiliation_string":"University of Erlangen\u2010N\u00fcrnberg ,","institution_ids":["https://openalex.org/I181369854"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5013051481"],"corresponding_institution_ids":[],"apc_list":{"value":5000,"currency":"EUR","value_usd":5392},"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.16479401,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"134","last_page":"145"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9983000159263611,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.8437551856040955},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8127683401107788},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7957915663719177},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.6710452437400818},{"id":"https://openalex.org/keywords/kernel","display_name":"Kernel (algebra)","score":0.5911003351211548},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.551535964012146},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.4953209459781647},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.478878915309906},{"id":"https://openalex.org/keywords/rapid-prototyping","display_name":"Rapid prototyping","score":0.46623939275741577},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.44438204169273376},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4387504458427429},{"id":"https://openalex.org/keywords/reconfigurable-computing","display_name":"Reconfigurable computing","score":0.424804151058197},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.4220614433288574},{"id":"https://openalex.org/keywords/fpga-prototype","display_name":"FPGA prototype","score":0.41202017664909363}],"concepts":[{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.8437551856040955},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8127683401107788},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7957915663719177},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.6710452437400818},{"id":"https://openalex.org/C74193536","wikidata":"https://www.wikidata.org/wiki/Q574844","display_name":"Kernel (algebra)","level":2,"score":0.5911003351211548},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.551535964012146},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.4953209459781647},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.478878915309906},{"id":"https://openalex.org/C2780395129","wikidata":"https://www.wikidata.org/wiki/Q1128971","display_name":"Rapid prototyping","level":2,"score":0.46623939275741577},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.44438204169273376},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4387504458427429},{"id":"https://openalex.org/C142962650","wikidata":"https://www.wikidata.org/wiki/Q240838","display_name":"Reconfigurable computing","level":3,"score":0.424804151058197},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.4220614433288574},{"id":"https://openalex.org/C203864433","wikidata":"https://www.wikidata.org/wiki/Q5426992","display_name":"FPGA prototype","level":3,"score":0.41202017664909363},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/3-540-57091-8_38","is_oa":false,"landing_page_url":"https://doi.org/10.1007/3-540-57091-8_38","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W2041938674","https://openalex.org/W2109488193","https://openalex.org/W2129261226","https://openalex.org/W3082313344","https://openalex.org/W6782264278"],"related_works":["https://openalex.org/W3002976045","https://openalex.org/W4247178515","https://openalex.org/W2097236935","https://openalex.org/W2121863986","https://openalex.org/W1843355381","https://openalex.org/W1492116303","https://openalex.org/W2069295582","https://openalex.org/W2101472307","https://openalex.org/W4360994686","https://openalex.org/W81273663"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}