{"id":"https://openalex.org/W1514001918","doi":"https://doi.org/10.1007/3-540-50728-0_53","title":"Application of graph theory to topology generation for logic gates","display_name":"Application of graph theory to topology generation for logic gates","publication_year":1989,"publication_date":"1989-01-01","ids":{"openalex":"https://openalex.org/W1514001918","doi":"https://doi.org/10.1007/3-540-50728-0_53","mag":"1514001918"},"language":"en","primary_location":{"id":"doi:10.1007/3-540-50728-0_53","is_oa":false,"landing_page_url":"https://doi.org/10.1007/3-540-50728-0_53","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},"type":"book-chapter","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5057947990","display_name":"Hubert Kaeslin","orcid":null},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":true,"raw_author_name":"Hubert Kaeslin","raw_affiliation_strings":["Integrated Systems Laboratory, Swiss Federal Institute of Technology, 8092, Z\u00fcrich, Switzerland","Swiss Federal Institute of Technology"],"affiliations":[{"raw_affiliation_string":"Integrated Systems Laboratory, Swiss Federal Institute of Technology, 8092, Z\u00fcrich, Switzerland","institution_ids":["https://openalex.org/I5124864"]},{"raw_affiliation_string":"Swiss Federal Institute of Technology","institution_ids":["https://openalex.org/I5124864"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5057947990"],"corresponding_institution_ids":["https://openalex.org/I5124864"],"apc_list":{"value":5000,"currency":"EUR","value_usd":5392},"apc_paid":null,"fwci":1.9777,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.8283968,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"304","last_page":"316"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10374","display_name":"Advanced Graph Theory Research","score":0.984499990940094,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12029","display_name":"DNA and Biological Computing","score":0.980400025844574,"subfield":{"id":"https://openalex.org/subfields/1312","display_name":"Molecular Biology"},"field":{"id":"https://openalex.org/fields/13","display_name":"Biochemistry, Genetics and Molecular Biology"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.7083999514579773},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.658014178276062},{"id":"https://openalex.org/keywords/graph-theory","display_name":"Graph theory","score":0.5743509531021118},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5366451740264893},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.5118919610977173},{"id":"https://openalex.org/keywords/boolean-function","display_name":"Boolean function","score":0.5002291202545166},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.4728058874607086},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.4436105489730835},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4225146472454071},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.29932698607444763},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2699623107910156},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.23329859972000122},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.19953593611717224},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.10612335801124573},{"id":"https://openalex.org/keywords/combinatorics","display_name":"Combinatorics","score":0.08773082494735718},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.07776454091072083}],"concepts":[{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.7083999514579773},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.658014178276062},{"id":"https://openalex.org/C88230418","wikidata":"https://www.wikidata.org/wiki/Q131476","display_name":"Graph theory","level":2,"score":0.5743509531021118},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5366451740264893},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.5118919610977173},{"id":"https://openalex.org/C187455244","wikidata":"https://www.wikidata.org/wiki/Q942353","display_name":"Boolean function","level":2,"score":0.5002291202545166},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.4728058874607086},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.4436105489730835},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4225146472454071},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.29932698607444763},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2699623107910156},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.23329859972000122},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.19953593611717224},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.10612335801124573},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.08773082494735718},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.07776454091072083},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/3-540-50728-0_53","is_oa":false,"landing_page_url":"https://doi.org/10.1007/3-540-50728-0_53","pdf_url":null,"source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320314140","display_name":"Family Process Institute","ror":null}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W53596869","https://openalex.org/W98901819","https://openalex.org/W1519532587","https://openalex.org/W1916505582","https://openalex.org/W1987067207","https://openalex.org/W2011039300","https://openalex.org/W2057084070","https://openalex.org/W2082355131","https://openalex.org/W2121655118","https://openalex.org/W2499438078","https://openalex.org/W3197565569","https://openalex.org/W4285719527","https://openalex.org/W6678226089"],"related_works":["https://openalex.org/W2086397253","https://openalex.org/W2133122801","https://openalex.org/W600422426","https://openalex.org/W2007156430","https://openalex.org/W2170882281","https://openalex.org/W3081478936","https://openalex.org/W1539291615","https://openalex.org/W3015089381","https://openalex.org/W1988224651","https://openalex.org/W2588941787"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
