{"id":"https://openalex.org/W1508905812","doi":"https://doi.org/10.1007/3-540-48311-x_175","title":"Instruction-Level Parallelism and Uniprocessor Architecture","display_name":"Instruction-Level Parallelism and Uniprocessor Architecture","publication_year":1999,"publication_date":"1999-01-01","ids":{"openalex":"https://openalex.org/W1508905812","doi":"https://doi.org/10.1007/3-540-48311-x_175","mag":"1508905812"},"language":"en","primary_location":{"id":"doi:10.1007/3-540-48311-x_175","is_oa":true,"landing_page_url":"https://doi.org/10.1007/3-540-48311-x_175","pdf_url":"https://link.springer.com/content/pdf/10.1007/3-540-48311-X_175.pdf","source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},"type":"book-chapter","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"bronze","oa_url":"https://link.springer.com/content/pdf/10.1007/3-540-48311-X_175.pdf","any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5084795370","display_name":"Pascal Sainrat","orcid":"https://orcid.org/0000-0003-1039-2290"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Pascal Sainrat","raw_affiliation_strings":[],"affiliations":[]},{"author_position":"last","author":{"id":"https://openalex.org/A5020844763","display_name":"Mateo Valero","orcid":"https://orcid.org/0000-0003-2917-2482"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Mateo Valero","raw_affiliation_strings":[],"affiliations":[]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5084795370"],"corresponding_institution_ids":[],"apc_list":{"value":5000,"currency":"EUR","value_usd":5392},"apc_paid":null,"fwci":0.0,"has_fulltext":true,"cited_by_count":0,"citation_normalized_percentile":{"value":0.12925969,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1241","last_page":"1242"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10715","display_name":"Distributed and Parallel Computing Systems","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9922999739646912,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.9083939790725708},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.7408972382545471},{"id":"https://openalex.org/keywords/uniprocessor-system","display_name":"Uniprocessor system","score":0.6772687435150146},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6033627390861511},{"id":"https://openalex.org/keywords/instruction-level-parallelism","display_name":"Instruction-level parallelism","score":0.5583460330963135},{"id":"https://openalex.org/keywords/compiler-correctness","display_name":"Compiler correctness","score":0.5520011186599731},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.5120590329170227},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.4285608232021332},{"id":"https://openalex.org/keywords/compiler-construction","display_name":"Compiler construction","score":0.4282287359237671},{"id":"https://openalex.org/keywords/interprocedural-optimization","display_name":"Interprocedural optimization","score":0.4207223057746887},{"id":"https://openalex.org/keywords/software-pipelining","display_name":"Software pipelining","score":0.414320170879364},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.3826860785484314},{"id":"https://openalex.org/keywords/parallelism","display_name":"Parallelism (grammar)","score":0.3466145396232605},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3370369076728821},{"id":"https://openalex.org/keywords/loop-optimization","display_name":"Loop optimization","score":0.19252365827560425},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.1763872504234314}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.9083939790725708},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.7408972382545471},{"id":"https://openalex.org/C79189994","wikidata":"https://www.wikidata.org/wiki/Q3488021","display_name":"Uniprocessor system","level":3,"score":0.6772687435150146},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6033627390861511},{"id":"https://openalex.org/C140763907","wikidata":"https://www.wikidata.org/wiki/Q2714055","display_name":"Instruction-level parallelism","level":3,"score":0.5583460330963135},{"id":"https://openalex.org/C68366613","wikidata":"https://www.wikidata.org/wiki/Q5156378","display_name":"Compiler correctness","level":3,"score":0.5520011186599731},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.5120590329170227},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.4285608232021332},{"id":"https://openalex.org/C9957790","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler construction","level":3,"score":0.4282287359237671},{"id":"https://openalex.org/C111564260","wikidata":"https://www.wikidata.org/wiki/Q4288856","display_name":"Interprocedural optimization","level":5,"score":0.4207223057746887},{"id":"https://openalex.org/C188854837","wikidata":"https://www.wikidata.org/wiki/Q268469","display_name":"Software pipelining","level":3,"score":0.414320170879364},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.3826860785484314},{"id":"https://openalex.org/C2781172179","wikidata":"https://www.wikidata.org/wiki/Q853109","display_name":"Parallelism (grammar)","level":2,"score":0.3466145396232605},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3370369076728821},{"id":"https://openalex.org/C29331672","wikidata":"https://www.wikidata.org/wiki/Q3354468","display_name":"Loop optimization","level":4,"score":0.19252365827560425},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.1763872504234314}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1007/3-540-48311-x_175","is_oa":true,"landing_page_url":"https://doi.org/10.1007/3-540-48311-x_175","pdf_url":"https://link.springer.com/content/pdf/10.1007/3-540-48311-X_175.pdf","source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"}],"best_oa_location":{"id":"doi:10.1007/3-540-48311-x_175","is_oa":true,"landing_page_url":"https://doi.org/10.1007/3-540-48311-x_175","pdf_url":"https://link.springer.com/content/pdf/10.1007/3-540-48311-X_175.pdf","source":{"id":"https://openalex.org/S106296714","display_name":"Lecture notes in computer science","issn_l":"0302-9743","issn":["0302-9743","1611-3349"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319900","host_organization_name":"Springer Science+Business Media","host_organization_lineage":["https://openalex.org/P4310319900","https://openalex.org/P4310319965"],"host_organization_lineage_names":["Springer Science+Business Media","Springer Nature"],"type":"book series"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Lecture Notes in Computer Science","raw_type":"book-chapter"},"sustainable_development_goals":[{"score":0.550000011920929,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":true,"grobid_xml":true},"content_urls":{"pdf":"https://content.openalex.org/works/W1508905812.pdf","grobid_xml":"https://content.openalex.org/works/W1508905812.grobid-xml"},"referenced_works_count":0,"referenced_works":[],"related_works":["https://openalex.org/W2094199724","https://openalex.org/W3000589862","https://openalex.org/W2169584677","https://openalex.org/W4232954277","https://openalex.org/W4240253816","https://openalex.org/W2901567138","https://openalex.org/W2354057234","https://openalex.org/W2749133591","https://openalex.org/W2066503869","https://openalex.org/W4246454774"],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
